7/8

STB75NH02L

High Side Switch (SW1)

Low Side Switch (SW2)

conduction

P

δ

*

I

*

R

2

L

DS(on)SW1

)

1

(

*

I

*

R

2

L

DS(on)SW2

δ

−

switching

P

g

L

I

I

*

f

*

)

Q

(Q

*

V

gd(SW1)

gsth(SW1)

in

+

Zero Voltage Switching

Recovery

Not Applicable

1

f

*

Q

*

V

rr(SW2)

in

diode

P

Conduction

Not Applicable

f

*

t

*

I

*

V

deadtime

L

f(SW2)

)

gate(Q

G

Pf

*

V

*

Q

gg

g(SW1)

f

*

V

*

Q

gg

gls(SW2)

Qoss

P

2

f

*

Q

*

V

oss(SW1)

in

2

f

*

Q

*

V

oss(SW2)

in

Appendix A: Buck Converter Power Losses Estimation

DESCRIPTION

The power losses associated with the FETs in a

Synchronous Buck converter can be estimated us-

ing the equations shown in the table below. The for-

mulas give a good approximation, for the sake of

performance comparison, of how different pairs of

devices affect the converter efficiency. However a

very important parameter, the working temperature,

is not considered. The real device behavior is really

dependent on how the heat generated inside the de-

vices is removed to allow for a safer working junc-

tion temperature.

The low side (SW2) device requires:

- Very low RDS(on) to reduce conduction losses

capaci tance

turn-on

especially with low drain to source voltage

to avoid the cross conduction phenomenon

The high side (SW1) device requires:

peak and to limit the voltage feedback on the gate

to reduce gate charge losses

Parameter

Meaning

δ

Duty-Cycle

Post Threshold Gate Charge

Third Quadrant Gate Charge

Pconduction

On State Losses

Pswitching

On-off Transition Losses

Pdiode

Conduction and Reverse Recovery Diode Losses

Pdiode

Gate Drive Losses

Output Capacitance Losses