S34ML01G1 数据表(PDF) 25 Page - Cypress Semiconductor
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Document Number: 002-00676 Rev. *V
Page 25 of 71
Multiplane Cache Program — S34ML02G1 and S34ML04G1
The Multiplane Cache Program enables high program throughput by programming two pages in parallel, while exploiting the data
and cache registers of both planes to implement cache.
The command sequence can be summarized as follows:
Serial Data Input command (80h), followed by the five cycle address inputs and then serial data for the 1st page. Address
for this page must be within 1st plane (PLA0 = 0). The data of 1st page other than those to be programmed do not need to
be loaded. The device supports Random Data Input exactly like Page Program operation.
The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes busy for a short
Once device returns to ready again, 81h command must be issued, followed by 2nd page address
(5 cycles) and its serial data input. Address for this page must be within 2nd plane (PLA0 = 1). The data of 2nd page other
than those to be programmed do not need to be loaded.
Cache Program confirm command (15h). Once the cache write command (15h) is loaded to the command register, the data
in the cache registers is transferred into the data registers for cell programming. At this time the device remains in the Busy
state for a short time (t
). After all data from the cache registers are transferred into the data registers, the device
returns to the Ready state, and allows loading the next data into the cache register through another Cache Program
The sequence 80h-...- 11h...-...81h...-...15h can be iterated, and each time the device will be busy for the t
time needed to
complete programming the current data register contents, and transferring the new data from the cache registers. The sequence to
end Multiplane Cache Program is 80h-...- 11h...-...81h...-...10h.
The Multiplane Cache Program is available only within two paired blocks in separate planes. Figure 39 on page 51 shows the legacy
protocol for the Multiplane Cache Program operation. In this case, the block address bits for the first plane are all zero and the
second address issued selects the block for both planes. Figure 40 on page 52 shows the ONFI protocol for the Multiplane Cache
Program operation. For both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that
select the plane.
The user can check operation status by R/B# pin or Read Status Register commands (70h or 78h). If the user opts for 70h, Read
Status Register will provide “global” information about the operation in the two planes.
I/O6 indicates when both cache registers are ready to accept new data.
I/O5 indicates when the cell programming of the current data registers is complete.
I/O1 identifies if the previous pages in both planes (pages N-1) have been successfully programmed or not. This status bit
is valid upon I/O6 status bit changing to 1.
I/O0 identifies if any error has been detected by the program/erase controller while programming the two pages N. This
status bit is valid upon I/O5 status bit changing to 1.
See Table 13 on page 22 for more details.
If the system monitors the progress of the operation only with R/B#, the last pages of the target program sequence must be
programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used instead, the status bit I/O5
must be polled to find out if the last programming is finished before starting any other operation. Refer to Section 3.9 on page 21 for
If a Multiplane Cache Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that
the interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are
complete for the applicable blocks.
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