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S34ML01G1 Datasheet(数据表) 24 Page - Cypress Semiconductor

部件型号  S34ML01G1
说明  1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
下载  71 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
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S34ML01G1 Datasheet(HTML) 24 Page - Cypress Semiconductor

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Document Number: 002-00676 Rev. *V
Page 24 of 71
S34ML01G1
S34ML02G1
S34ML04G1
3.14
Cache Program
Cache Program can improve the program throughput by using the cache register. The Cache Program operation cannot cross a
block boundary. The cache register allows new data to be input while the previous data that was transferred to the data register is
programmed into the memory array.
After the serial data input command (80h) is loaded to the command register, followed by five cycles of address, a full or partial page
of data is latched into the cache register.
Once the cache write command (15h) is loaded to the command register, the data in the cache register is transferred into the data
register for cell programming. At this time the device remains in the Busy state for a short time (tCBSYW). After all data of the cache
register is transferred into the data register, the device returns to the Ready state and allows loading the next data into the cache
register through another Cache Program command sequence (80h-15h).
The Busy time following the first sequence 80h - 15h equals the time needed to transfer the data from the cache register to the data
register. Cell programming the data of the data register and loading of the next data into the cache register is consequently
processed through a pipeline model.
In case of any subsequent sequence 80h - 15h, transfer from the cache register to the data register is held off until cell programming
of current data register contents is complete; till this moment the device will stay in a busy state (tCBSYW).
Read Status commands (70h or 78h) may be issued to check the status of the different registers, and the pass/fail status of the
cached program operations.
The Cache-Busy status bit I/O6 indicates when the cache register is ready to accept new data.
The status bit I/O5 can be used to determine when the cell programming of the current data register contents is complete.
The Cache Program error bit I/O1 can be used to identify if the previous page (page N-1) has been successfully
programmed or not in a Cache Program operation. The status bit is valid upon I/O6 status bit changing to 1.
The error bit I/O0 is used to identify if any error has been detected by the program/erase controller while programming page
N. The status bit is valid upon I/O5 status bit changing to 1.
I/O1 may be read together with I/O0.
If the system monitors the progress of the operation only with R/B#, the last page of the target program sequence must be
programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used instead, the status bit I/O5
must be polled to find out if the last programming is finished before starting any other operation. See Table 13 on page 22 and
Figure 38 on page 50 for more details.
If a Cache Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete
for the applicable blocks.




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