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S34ML01G1 Datasheet(数据表) 23 Page - Cypress Semiconductor

部件型号  S34ML01G1
说明  1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
下载  71 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
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S34ML01G1 Datasheet(HTML) 23 Page - Cypress Semiconductor

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Document Number: 002-00676 Rev. *V
Page 23 of 71
S34ML01G1
S34ML02G1
S34ML04G1
3.13
Read Cache
Read Cache can be used to increase the read operation speed, as defined in Section 3.1 on page 15, and it cannot cross a block
boundary. As soon as the user starts to read one page, the device automatically loads the next page into the cache register. Serial
data output may be executed while data in the memory is read into the cache register. Read Cache is initiated by the Page Read
sequence (00-30h) on a page M.
After random access to the first page is complete (R/B# returned to high, or Read Status Register I/O6 switches to high), two
command sequences can be used to continue read cache:
Read Cache (command ‘31h’ only): once the command is latched into the command register (see Figure 35 on page 49),
device goes busy for a short time (tCBSYR), during which data of the first page is transferred from the data register to the
cache register. At the end of this phase, the cache register data can be output by toggling RE# while the next page (page
address M+1) is read from the memory array into the data register.
Read Cache Enhanced (sequence ‘00h’ <page N address> ‘31’): once the command is latched into the command register
(see Figure 36 on page 50), device goes busy for a short time (tCBSYR), during which data of the first page is transferred
from the data register to the cache register. At the end of this phase, cache register data can be output by toggling RE#
while page N is read from the memory array into the data register.
Note: The S34ML01G1 device does not support Read Cache Enhanced.
Subsequent pages are read by issuing additional Read Cache or Read Cache Enhanced command sequences. If serial data output
time of one page exceeds random access time (tR), the random access time of the next page is hidden by data downloading of the
previous page.
On the other hand, if 31h is issued prior to completing the random access to the next page, the device will stay busy as long as
needed to complete random access to this page, transfer its contents into the cache register, and trigger the random access to the
following page.
To terminate the Read Cache operation, 3Fh command should be issued (see Figure 37 on page 50). This command transfers data
from the data register to the cache register without issuing next page read.
During the Read Cache operation, the device doesn't allow any other command except for 00h, 31h, 3Fh, Read SR, or Reset (FFh).
To carry out other operations, Read Cache must be terminated by the Read Cache End command (3Fh) or the device must be reset
by issuing FFh.
Read Status command (70h) may be issued to check the status of the different registers and the busy/ready status of the cached
read operations.
The Cache-Busy status bit I/O6 indicates when the cache register is ready to output new data.
The status bit I/O5 can be used to determine when the cell reading of the current data register contents is complete.
Note: The Read Cache and Read Cache End commands reset the column counter, thus, when RE# is toggled to output the data of
a given page, the first output data is related to the first byte of the page (column address 00h). Random Data Output command can
be used to switch column address.




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