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S34ML01G1 Datasheet(数据表) 22 Page - Cypress Semiconductor

部件型号  S34ML01G1
说明  1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
下载  71 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
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S34ML01G1 Datasheet(HTML) 22 Page - Cypress Semiconductor

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Document Number: 002-00676 Rev. *V
Page 22 of 71
S34ML01G1
S34ML02G1
S34ML04G1
3.10
Read Status Enhanced — S34ML02G1 and S34ML04G1
Read Status Enhanced is used to retrieve the status value for a previous operation in the specified plane.
Figure 32 on page 48 defines the Read Status Enhanced behavior and timings. The plane and die address must be specified in the
command sequence in order to retrieve the status of the die and the plane of interest.
Refer to Table 13 for specific Status Register definitions. The command register remains in Status Read mode until further
commands are issued.
The Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.
3.11
Read Status Register Field Definition
Table 13 below lists the meaning of each bit of the Read Status Register and Read Status Enhanced (S34ML02G1 and
S34ML04G1).
3.12
Reset
The Reset feature is executed by writing FFh to the command register. If the device is in the Busy state during random read,
program, or erase mode, the Reset operation will abort these operations. The contents of memory cells being altered are no longer
valid, as the data may be partially programmed or erased. The command register is cleared to wait for the next command, and the
Status Register is cleared to value E0h when WP# is high or value 60h when WP# is low. If the device is already in reset state a new
Reset command will not be accepted by the command register. The R/B# pin transitions to low for tRST after the Reset command is
written. Refer to Figure 33 on page 48 for further details. The Status Register can also be read to determine the status of a Reset
operation.
Table 13. Status Register Coding
ID
Page Program /
Page Reprogram
Block Erase
Read
Read Cache
Cache Program /
Cache Reprogram
Coding
0
Pass / Fail
Pass / Fail
NA
NA
Pass / Fail
N Page
Pass: 0
Fail: 1
1
NA
NA
NA
NA
Pass / Fail
N - 1 Page
Pass: 0
Fail: 1
2NA
NA
NA
NA
NA
3NA
NA
NA
NA
NA
4NA
NA
NA
NA
NA
5
Ready / Busy
Ready / Busy Ready / Busy Ready / Busy
Ready / Busy
Internal Data Operation Active: 0
Idle: 1
6
Ready / Busy
Ready / Busy Ready / Busy Ready / Busy
Ready / Busy
Ready / Busy
Busy: 0
Ready: 1
7
Write Protect
Write Protect
NA
NA
Write Protect
Protected: 0
Not Protected: 1




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