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S34ML01G1 Datasheet(数据表) 21 Page - Cypress Semiconductor

部件型号  S34ML01G1
说明  1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
下载  71 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
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S34ML01G1 Datasheet(HTML) 21 Page - Cypress Semiconductor

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Document Number: 002-00676 Rev. *V
Page 21 of 71
S34ML01G1
S34ML02G1
S34ML04G1
3.9
Read Status Register
The Status Register is used to retrieve the status value for the last operation issued. After writing 70h command to the command
register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs
last. This two-line control allows the system to poll the progress of each device in multiple memory connections even when R/B#
pins are common-wired. Refer to Section 13 on page 22 for specific Status Register definition, and to Figure 31 on page 48 for
timings.
If the Read Status Register command is issued during multiplane operations then Status Register polling will return the combined
status value related to the outcome of the operation in the two planes according to the following table.
In other words, the Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.
The command register remains in Status Read mode until further commands are issued. Therefore, if the Status Register is read
during a random read cycle, the read command (00h) must be issued before starting read cycles.
Note: The Read Status Register command shall not be used for concurrent operations in multi-die stack configurations (single CE#).
“Read Status Enhanced” shall be used instead.
Table 10. Page Organization in EDC Units
Main Field (2048 Byte)
Spare Field (64 Byte)
“A” area
(1st sector)
“B” area
(2nd sector)
“C” area
(3rd sector)
“D” area
(4th sector)
“E” area
(1st sector)
“F” area
(2nd sector)
“G” area
(3rd sector)
“H” area
(4th sector)
×8
512 byte
512 byte
512 byte
512 byte
16 byte
16 byte
16 byte
16 byte
×16
256 words
256 words
256 words
256 words
8 words
8 words
8 words
8 words
Table 11. Page Organization in EDC Units by Address
Sector
Main Field (Column 0-2047)
Spare Field (Column 2048-2111)
Area Name
Column Address
Area Name
Column Address
×8
1st 528-byte Sector
A
0-511
E
2048-2063
2nd 528-byte Sector
B
512-1023
F
2064-2079
3rd 528-byte Sector
C
1024-1535
G
2080-2095
4th 528-byte Sector
D
1536-2047
H
2096-2111
×16
1st 256-word Sector
A
0-255
E
1024-1031
2nd 256-word Sector
B
256-511
F
1032-1039
3rd 256-word Sector
C
512-767
G
1040-1047
4th 256-word Sector
D
768-1023
H
1048-1055
Table 12. Read Status Definition
Status Register Bit
Composite Status Value
Bit 0, Pass/Fail
OR
Bit 1, Cache Pass/Fail
OR




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