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S34ML01G1 Datasheet(数据表) 20 Page - Cypress Semiconductor

部件型号  S34ML01G1
说明  1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
下载  71 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
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S34ML01G1 Datasheet(HTML) 20 Page - Cypress Semiconductor

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Document Number: 002-00676 Rev. *V
Page 20 of 71
S34ML01G1
S34ML02G1
S34ML04G1
For the case of Page Program, Multiplane Page Program, Page Reprogram, Multiplane Page Reprogram, Cache Program, and
Multiplane Cache Program operations:
In Section3.2 onpage 15 it was explained that a number of consecutive partial program operations (NOP) is allowed within
the same page. In case this feature is used, the number of partial program operations occurring in the same EDC unit must
not exceed 1. In other words, page program operations must be performed on the whole page, or on whole EDC unit at a
time.
“Random Data Input” in a given EDC unit can be executed several times during one page program sequence, but data
cannot be written to any column address more than once before the program is initiated.
For the case of Copy Back Program or Multiplane Copy Back Program operations:
If Random Data Input is applied in a given EDC unit, the entire EDC unit must be written to the page buffer. In other words,
the EDC check is possible only if the whole EDC unit is modified during one Copy Back Program sequence.
“Random Data Input” in a given EDC unit can be executed several times during one Copy Back Program sequence, but
data insertion in each column address of the EDC unit must not exceed 1.
If you use copy back without EDC check, none of the limitations described above apply.
After a Copy Back Program operation, the host can use Read EDC Status Register to check the status of both the program
operation and the Copy Back Read. If the EDC was valid and an error was reported in the EDC (see Table 9 on page 20), the host
may perform Special Read For Copy Back on the source page and attempt the Copy Back Program again. If this also fails, the host
can execute a Page Read operation in order to correct a single bit error with external ECC software or hardware.
3.8.1
Read EDC Status Register — S34ML02G1 and S34ML04G1
This operation is available only after issuing a Copy Back Program and it allows the detection of errors during Copy Back Read. In
the case of multiplane copy back, it is not possible to know which of the two read operations caused the error.
After writing the Read EDC Status Register command (7Bh) to the command register, a read cycle outputs the content of the EDC
Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs last.
The operation is the same as the Read Status Register command. Refer to Table 9 for specific EDC Register definitions:
Table 9. EDC Register Coding
ID
Copy Back Program
Coding
0
Pass / Fail
Pass: 0; Fail: 1
1
EDC status
No error: 0; Error: 1
2
EDC validity
Invalid: 0; Valid: 1
3NA
4NA
5
Ready / Busy
Busy: 0; Ready: 1
6
Ready / Busy
Busy: 0; Ready: 1
7
Write Protect
Protected: 0; Not Protected: 1




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