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S34ML01G1 Datasheet(数据表) 2 Page - Cypress Semiconductor

部件型号  S34ML01G1
说明  1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
下载  71 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
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S34ML01G1 Datasheet(HTML) 2 Page - Cypress Semiconductor

 
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Document Number: 002-00676 Rev. *V
Page 2 of 71
S34ML01G1
S34ML02G1
S34ML04G1
Contents
1.
General Description..................................................... 4
1.1 Logic Diagram................................................................ 5
1.2 Connection Diagram ...................................................... 6
1.3 Pin Description............................................................... 7
1.4 Block Diagram................................................................ 8
1.5 Array Organization ......................................................... 9
1.6 Addressing ................................................................... 10
1.7 Mode Selection ............................................................ 12
2.
Bus Operation ............................................................ 13
2.1 Command Input ........................................................... 13
2.2 Address Input............................................................... 13
2.3 Data Input .................................................................... 13
2.4 Data Output.................................................................. 13
2.5 Write Protect ................................................................ 13
2.6 Standby........................................................................ 13
3.
Command Set............................................................. 14
3.1 Page Read ................................................................... 15
3.2 Page Program.............................................................. 15
3.3 Multiplane Program
— S34ML02G1 and S34ML04G1 ................................ 16
3.4 Page Reprogram
— S34ML02G1 and S34ML04G1 ................................ 16
3.5 Block Erase.................................................................. 18
3.6 Multiplane Block Erase
— S34ML02G1 and S34ML04G1 ................................ 18
3.7 Copy Back Program..................................................... 18
3.8 EDC Operation — S34ML02G1 and S34ML04G1....... 19
3.9 Read Status Register................................................... 21
3.10 Read Status Enhanced
— S34ML02G1 and S34ML04G1 ................................ 22
3.11 Read Status Register Field Definition .......................... 22
3.12 Reset............................................................................ 22
3.13 Read Cache ................................................................. 23
3.14 Cache Program............................................................ 24
3.15 Multiplane Cache Program
— S34ML02G1 and S34ML04G1 ................................ 25
3.16 Read ID........................................................................ 26
3.17 Read ID2...................................................................... 29
3.18 Read ONFI Signature .................................................. 29
3.19 Read Parameter Page ................................................. 29
3.20 One-Time Programmable (OTP) Entry ........................ 31
4.
Signal Descriptions ................................................... 32
4.1 Data Protection and Power On / Off Sequence ........... 32
4.2 Ready/Busy.................................................................. 32
4.3 Write Protect Operation ............................................... 33
5.
Electrical Characteristics .......................................... 34
5.1 Valid Blocks ................................................................. 34
5.2 Absolute Maximum Ratings ......................................... 34
5.3 Recommended Operating Conditions.......................... 34
5.4 AC Test Conditions ...................................................... 34
5.5 AC Characteristics ....................................................... 35
5.6 DC Characteristics ....................................................... 36
5.7 Pin Capacitance........................................................... 36
5.8 Thermal Resistance...................................................... 37
5.9 Program / Erase Characteristics................................... 37
6.
Timing Diagrams......................................................... 38
6.1 Command Latch Cycle.................................................. 38
6.2 Address Latch Cycle..................................................... 38
6.3 Data Input Cycle Timing................................................ 39
6.4 Data Output Cycle Timing
(CLE=L, WE#=H, ALE=L, WP#=H)............................... 39
6.5 Data Output Cycle Timing
(EDO Type, CLE=L, WE#=H, ALE=L) .......................... 40
6.6 Page Read Operation ................................................... 40
6.7 Page Read Operation (Interrupted by CE#).................. 41
6.8 Page Read Operation Timing with CE# Don’t Care...... 41
6.9 Page Program Operation.............................................. 42
6.10 Page Program Operation Timing
with CE# Don’t Care ..................................................... 42
6.11 Page Program Operation with Random Data Input ...... 43
6.12 Random Data Output In a Page ................................... 43
6.13 Multiplane Page Program Operation
— S34ML02G1 and S34ML04G1................................. 44
6.14 Block Erase Operation.................................................. 45
6.15 Multiplane Block Erase
— S34ML02G1 and S34ML04G1................................. 45
6.16 Copy Back Read with Optional Data Readout.............. 46
6.17 Copy Back Program Operation
With Random Data Input............................................... 46
6.18 Multiplane Copy Back Program
— S34ML02G1 and S34ML04G1................................. 47
6.19 Read Status Register Timing........................................ 48
6.20 Read Status Enhanced Timing ..................................... 48
6.21 Reset Operation Timing................................................ 48
6.22 Read Cache.................................................................. 49
6.23 Cache Program............................................................. 50
6.24 Multiplane Cache Program
— S34ML02G1 and S34ML04G1................................. 51
6.25 Read ID Operation Timing ............................................ 53
6.26 Read ID2 Operation Timing .......................................... 53
6.27 Read ONFI Signature Timing........................................ 54
6.28 Read Parameter Page Timing ...................................... 54
6.29 OTP Entry Timing ......................................................... 54
6.30 Power On and Data Protection Timing ......................... 55
6.31 WP# Handling............................................................... 55
7.
Physical Interface ....................................................... 56
7.1 Physical Diagram.......................................................... 56
8.
System Interface ......................................................... 58
9.
Error Management ...................................................... 59
9.1 System Bad Block Replacement................................... 59
9.2 Bad Block Management................................................ 60
10. Ordering Information.................................................. 61
11. Document History Page ............................................. 62




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