S34ML01G1 数据表(PDF) 18 Page - Cypress Semiconductor
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S34ML01G1 数据表(HTML) 18 Page - Cypress Semiconductor
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Document Number: 002-00676 Rev. *V
Page 18 of 71
The Block Erase operation is done on a block basis. Block address loading is accomplished in three cycles (two cycles for
S34ML01G1) initiated by an Erase Setup command (60h). Only the block address bits are valid while the page address bits are
The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step
sequence of setup followed by the execution command ensures that memory contents are not accidentally erased due to external
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and erase verify. Once
the erase process starts, the Read Status Register commands (70h or 78h) may be issued to read the Status Register.
The system controller can detect the completion of an erase by monitoring the R/B# output, or the Status bit (I/O6) of the Status
Register. Only the Read Status commands (70h or 78h) and Reset command are valid while erasing is in progress. When the erase
operation is completed, the Write Status Bit (I/O0) may be checked. Figure 24 on page 45 details the sequence.
If a Block Erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted
block is erased under continuous power conditions before that block can be trusted for further programming and reading operations.
Multiplane Block Erase — S34ML02G1 and S34ML04G1
Multiplane Block Erase allows the erase of two blocks in parallel, one block per memory plane.
The Block erase setup command (60h) must be repeated two times, followed by 1st and 2nd block address respectively (3 cycles
each). As for block erase, D0h command makes embedded operation start. In this case, multiplane erase does not need any
Dummy Busy Time between 1st and 2nd block insertion. See Table 23 on page 37 for performance information.
For the Multiplane Block Erase operation, the address of the first block must be within the first plane (PLA0 = 0) and the address of
the second block in the second plane (PLA0 = 1). See Figure 25 on page 45 for a description of the legacy protocol. In this case, the
block address bits for the first plane are all zero and the second address issued selects the block for both planes. Figure 26
on page 46 describes the sequences using the ONFI protocol. For both addresses issued in this protocol, the block address bits
must be the same except for the bit(s) that select the plane.
The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or 78h). The Read Status
Register command is also available during Dummy Busy time (t
). In case of failure in either erase, the fail bit of the Status
Register will be set. Refer to Section 3.9 on page 21 for further information.
If a Multiplane Block Erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted blocks are erased under continuous power conditions before those blocks can be trusted for further programming and
Copy Back Program
The copy back feature is intended to quickly and efficiently rewrite data stored in one page without utilizing an external memory.
Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is greatly improved.
The benefit is especially obvious when a portion of a block needs to be updated and the rest of the block also needs to be copied to
the newly assigned free block. The operation for performing a copy back is a sequential execution of page-read (without mandatory
serial access) and Copy Back Program with the address of destination page. A read operation with the ‘35h’ command and the
address of the source page moves the whole page of data into the internal data register. As soon as the device returns to the Ready
state, optional data read-out is allowed by toggling RE# (see Figure 27 on page 46), or the Copy Back Program command (85h) with
the address cycles of the destination page may be written. The Program Confirm command (10h) is required to actually begin
The source and the destination pages in the Copy Back Program sequence must belong to the same device plane (same PLA0 for
S34ML02G1 and S34ML04G1). Copy Back Read and Copy Back Program for a given plane must be between odd address pages or
between even address pages for the device to meet the program time (t
) specification. Copy Back Program may not meet this
specification when copying from an odd address page (source page) to an even address page (target page) or from an even
address page (source page) to an odd address page (target page).
The data input cycle for modifying a portion or multiple distinct portions of the source page is allowed as shown in Figure 28
on page 46. As noted in Section 1. on page 4 the device may include an automatic EDC (for S34ML02G1 and S34ML04G1) check
during the copy back operation, to detect single bit errors in EDC units contained within the source page. More details on EDC
operation and limitations related to data input handling during one Copy Back Program sequence are available in Section 3.8
on page 19.
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