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S34ML01G1 Datasheet(数据表) 17 Page - Cypress Semiconductor

部件型号  S34ML01G1
说明  1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
下载  71 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
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S34ML01G1 Datasheet(HTML) 17 Page - Cypress Semiconductor

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 17 page
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Document Number: 002-00676 Rev. *V
Page 17 of 71
S34ML01G1
S34ML02G1
S34ML04G1
On the other hand, if the pattern bound for the target page is different from that of the previous page, data in cycles can be issued
before program confirm ‘10h’, as described in Figure 9.
Figure 9. Page Reprogram with Data Manipulation
The device supports Random Data Input within a page. The column address of next data, which will be entered, may be changed to
the address which follows the Random Data Input command (85h). Random Data Input may be operated multiple times regardless
of how many times it is done in a page.
The Program Confirm command (10h) initiates the re-programming process. The internal write state controller automatically
executes the algorithms and controls timings necessary for program and verify, thereby freeing the system controller for other tasks.
Once the program process starts, the Read Status Register command may be issued to read the Status Register. The system
controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register.
Only the Read Status command and Reset command are valid when programming is in progress. When the Page Program is
complete, the Write Status Bit (I/O0) may be checked. The internal write verify detects only errors for 1’s that are not successfully
programmed to 0’s. The command register remains in Read Status command mode until another valid command is written to the
command register.
The Page Reprogram must be issued in the same plane as the Page Program that failed. In order to program the data to a different
plane, use the Page Program operation instead. The Multiplane Page Reprogram can re-program two pages in parallel, one per
plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The command
sequence is very similar to Figure 22 on page 44, except that it requires the Page Reprogram Command (8Bh) instead of 80h and
81h.
If a Page Reprogram operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete.
C1
IOx
SR[6]
SR[6]
Cycle Type
I/Ox
Cycle Type
As defined for Page
Program
A
A
CMD
ADDR
ADDR
ADDR
ADDR
80h
C2
R1
R3
Page N
Din
Din
Din
Din
CMD
D0
D1
. . .
Dn
10h
CMD
ADDR
ADDR
ADDR
ADDR
8Bh
C1
C2
R1
R3
FAIL !
Page M
CMD
10h
tADL
tWB
tPROG
tWB
tPROG
CMD
Dout
70h
E1
Din
Din
Din
Din
D0
D1
. . .
Dn
tADL
ADDR
R2
ADDR
R2




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