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S34ML01G1 Datasheet(数据表) 16 Page - Cypress Semiconductor

部件型号  S34ML01G1
说明  1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
下载  71 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
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S34ML01G1 Datasheet(HTML) 16 Page - Cypress Semiconductor

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Document Number: 002-00676 Rev. *V
Page 16 of 71
S34ML01G1
S34ML02G1
S34ML04G1
3.3
Multiplane Program — S34ML02G1 and S34ML04G1
The S34ML02G1 and S34ML04G1 devices support Multiplane Program, making it possible to program two pages in parallel, one
page per plane.
A Multiplane Program cycle consists of a double serial data loading period in which up to 4224 bytes (×8) or 2112 words (×16) of
data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into
the appropriate cell. The serial data loading period begins with inputting the Serial Data Input command (80h), followed by the five
cycle address inputs and serial data for the 1st page. The address for this page must be in the 1st plane (PLA0 = 0). The device
supports Random Data Input exactly the same as in the case of page program operation. The Dummy Page Program Confirm
command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has become ready again,
the ‘81h’ command must be issued, followed by 2nd page address (5 cycles) and its serial data input. The address for this page
must be in the 2nd plane (PLA0 = 1). The Program Confirm command (10h) starts parallel programming of both pages.
Figure 22 on page 44 describes the sequences using the legacy protocol. In this case, the block address bits for the first plane are
all zero and the second address issued selects the block for both planes. Figure 23 on page 44 describes the sequences using the
ONFI protocol. For both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select
the plane.
The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or 78h). The Read Status
Register command is also available during Dummy Busy time (tDBSY). In case of failure in either page program, the fail bit of the
Status Register will be set. Refer to Section 3.9 on page 21 for further info.
The number of consecutive partial page programming operations (NOP) within the same page must not exceed the number
indicated in Table 23 on page 37. Pages may be programmed in any order within a block.
If a Multiplane Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete
for the applicable blocks.
3.4
Page Reprogram — S34ML02G1 and S34ML04G1
Page Program may result in a fail, which can be detected by Read Status Register. In this event, the host may call Page Reprogram.
This command allows the reprogramming of the same pattern of the last (failed) page into another memory location. The command
sequence initiates with reprogram setup (8Bh), followed by the five cycle address inputs of the target page. If the target pattern for
the destination page is not changed compared to the last page, the program confirm can be issued (10h) without any data input
cycle, as described in Figure 8.
Figure 8. Page Reprogram
SR[6]
I/Ox
Cycle Type
As defined for Page
Program
A
A
C1
I/Ox
SR[6]
Cycle Type
CMD
ADDR
ADDR
ADDR
00h
C2
R1
R3
Page N
Din
Din
Din
Din
CMD
D0
D1
. . .
Dn
10h
CMD
Dout
70h
E1
FAIL !
Page M
CMD
10h
tADL
tWB
tPROG
tWB
tPROG
ADDR
R2
ADDR
CMD
ADDR
ADDR
ADDR
ADDR
ADDR
8Bh
C1
C2
R1
R3
R2




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