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S34ML01G1 Datasheet(数据表) 15 Page - Cypress Semiconductor

部件型号  S34ML01G1
说明  1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
下载  71 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
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S34ML01G1 Datasheet(HTML) 15 Page - Cypress Semiconductor

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Document Number: 002-00676 Rev. *V
Page 15 of 71
S34ML01G1
S34ML02G1
S34ML04G1
3.1
Page Read
Page Read is initiated by writing 00h and 30h to the command register along with five address cycles (four or five cycles for
S34ML01G1). Two types of operations are available: random read and serial page read. Random read mode is enabled when the
page address is changed. All data within the selected page are transferred to the data registers. The system controller may detect
the completion of this data transfer (tR) by analyzing the output of the R/B pin. Once the data in a page is loaded into the data
registers, they may be read out in 25 ns cycle time by sequentially pulsing RE#. The repetitive high to low transitions of the RE#
signal makes the device output the data, starting from the selected column address up to the last column address.
The device may output random data in a page instead of the sequential data by writing Random Data Output command. The column
address of next data, which is going to be out, may be changed to the address that follows Random Data Output command. Random
Data Output can be performed as many times as needed.
After power up, the device is in read mode, so 00h command cycle is not necessary to start a read operation. Any operation other
than read or Random Data Output causes the device to exit read mode. See Figure 6.1 on page 40 and Figure 21 on page 43 as
references.
3.2
Page Program
A page program cycle consists of a serial data loading period in which up to 2112 bytes (×8) or 1056 words (×16) of data may be
loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the
appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle address inputs
(four cycles for S34ML01G1) and then serial data. The words other than those to be programmed do not need to be loaded. The
device supports Random Data Input within a page. The column address of next data, which will be entered, may be changed to the
address that follows the Random Data Input command (85h). Random Data Input may be performed as many times as needed.
The Page Program confirm command (10h) initiates the programming process. The internal write state controller automatically
executes the algorithms and controls timings necessary for program and verify, thereby freeing the system controller for other tasks.
Once the program process starts, the Read Status Register commands (70h or 78h) may be issued to read the Status Register. The
system controller can detect the completion of a program cycle by monitoring the
R/B# output, or the Status bit (I/O6) of the Status Register. Only the Read Status commands (70h or 78h) or Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O0) may be checked. The
internal write verify detects only errors for 1’s that are not successfully programmed to 0’s. The command register remains in Read
Status command mode until another valid command is written to the command register. Figure6.2 onpage42 and Figure 20
on page 43 detail the sequence.
The device is programmable by page, but it also allows multiple partial page programming of a word or consecutive bytes up to 2112
bytes (×8) or 1056 words (×16) in a single page program cycle.
The number of consecutive partial page programming operations (NOP) within the same page must not exceed the number
indicated in Table 23 on page 37. Pages may be programmed in any order within a block.
Users who use “EDC check” (for S34ML02G1 and S34ML04G1 only) in copy back must comply with some limitations related to data
handling during one page program sequence. Refer to Section 3.8 on page 19 for details.
If a Page Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete.




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