S34ML01G1 Datasheet(数据表) 13 Page - Cypress Semiconductor
CYPRESS [Cypress Semiconductor]
S34ML01G1 Datasheet(HTML) 13 Page - Cypress Semiconductor
Document Number: 002-00676 Rev. *V
Page 13 of 71
2. Bus Operation
There are six standard bus operations that control the device: Command Input, Address Input, Data Input, Data Output, Write
Protect, and Standby. (See Table 7.)
Typically glitches less than 5 ns on Chip Enable, Write Enable, and Read Enable are ignored by the memory and do not affect bus
The Command Input bus operation is used to give a command to the memory device. Commands are accepted with Chip Enable
low, Command Latch Enable high, Address Latch Enable low, and Read Enable high and latched on the rising edge of Write Enable.
Moreover, for commands that start a modify operation (program/erase) the Write Protect pin must be high. See Figure 12
on page 38 and Table 20 on page 35 for details of the timing requirements. Command codes are always applied on I/O7:0
regardless of the bus configuration (×8 or ×16).
The Address Input bus operation allows the insertion of the memory address. For the S34ML02G1 and S34ML04G1 devices, five
write cycles are needed to input the addresses. For the S34ML01G1, four write cycles are needed to input the addresses. If
necessary, a 5th dummy address cycle can be issued to S34ML01G1, which will be ignored by the NAND device without causing
problems. Addresses are accepted with Chip Enable low, Address Latch Enable high, Command Latch Enable low, and Read
Enable high and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation (program/erase)
the Write Protect pin must be high. See Figure 13 on page 38 and Table 20 on page 35 for details of the timing requirements.
Addresses are always applied on I/O7:0 regardless of the bus configuration (×8 or ×16). Refer to Table 4 through Table 6
on page 11 for more detailed information.
The Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is serial and timed by
the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read
Enable high, and Write Protect high and latched on the rising edge of Write Enable. See Figure 14 on page 39 and Table 20
on page 35 for details of the timing requirements.
The Data Output bus operation allows data to be read from the memory array and to check the Status Register content, the EDC
register content, and the ID data. Data can be serially shifted out by toggling the Read Enable pin with Chip Enable low, Write
Enable high, Address Latch Enable low, and Command Latch Enable low. See Figure 15 on page 39 and Table 20 on page 35 for
details of the timings requirements.
The Hardware Write Protection is activated when the Write Protect pin is low. In this condition, modify operations do not start and the
content of the memory is not altered. The Write Protect pin is not latched by Write Enable to ensure the protection even during power
In Standby, the device is deselected, outputs are disabled, and power consumption is reduced.
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