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S34ML01G1 Datasheet(数据表) 7 Page - Cypress Semiconductor

部件型号  S34ML01G1
说明  1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
下载  71 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
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S34ML01G1 Datasheet(HTML) 7 Page - Cypress Semiconductor

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Document Number: 002-00676 Rev. *V
Page 7 of 71
S34ML01G1
S34ML02G1
S34ML04G1
Figure 4. 63-BGA Contact, ×16 Device (Balls Down, Top View)
1.3
Pin Description
Notes
2. A 0.1 µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB
track widths must be sufficient to carry the currents required during program and erase operations.
3. An internal voltage detector disables all functions whenever VCC is below 1.8V to protect the device from any involuntary program/erase during power transitions.
Table 3. Pin Description
Pin Name
Description
I/O0 - I/O7 (×8)
Inputs/Outputs. The I/O pins are used for command input, address input, data input, and data output. The I/O pins float
to High-Z when the device is deselected or the outputs are disabled.
I/O8 - I/O15 (×16)
CLE
Command Latch Enable. This input activates the latching of the I/O inputs inside the Command Register on the rising
edge of Write Enable (WE#).
ALE
Address Latch Enable. This input activates the latching of the I/O inputs inside the Address Register on the rising edge
of Write Enable (WE#).
CE#
Chip Enable. This input controls the selection of the device. When the device is not busy CE# low selects the memory.
WE#
Write Enable. This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of WE#.
RE#
Read Enable. The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE# which also increments the internal column address counter by one.
WP#
Write Protect. The WP# pin, when low, provides hardware protection against undesired data modification (program /
erase).
R/B#
Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC
Supply Voltage. The VCC supplies the power for all the operations (Read, Program, Erase). An internal lock circuit
prevents the insertion of Commands when VCC is less than VLKO.
VSS
Ground.
NC
Not Connected.
F3
F4
F5
F6
F7
F8
E3
E4
E5
E6
E7
E8
D3
D4
D5
D6
D7
D8
C3
C4
C5
C6
C7
C8
RB#
WE#
CE#
VSS
ALE
WP#
NC
NC
NC
CLE
RE#
VCC
NC
NC
NC
NC
NC
NC
G3
G4
G5
G6
G7
G8
NC
VSS
NC
NC
NC
NC
H3
H4
H5
H6
H7
H8
Vcc
I/O14
I/O12
I/O10
I/O0
I/O8
B9
A9
NC
NC
A2
NC
NC
I/O15
I/O13
NC
VCC
NC
B10
A10
NC
NC
B1
A1
NC
NC
J3
J4
J5
J6
J7
J8
I/O7
I/O5
VCC
I/O11
I/O1
I/O9
K3
K4
K5
K6
K7
K8
VSS
I/O6
I/O4
I/O3
I/O2
VSS
L9
NC
L2
NC
L10
NC
L1
NC
M9
NC
M2
NC
M10
NC
M1
NC




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