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S34ML01G1 Datasheet(数据表) 47 Page - Cypress Semiconductor

部件型号  S34ML01G1
说明  1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
下载  71 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
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S34ML01G1 Datasheet(HTML) 47 Page - Cypress Semiconductor

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Document Number: 002-00676 Rev. *V
Page 47 of 71
S34ML01G1
S34ML02G1
S34ML04G1
6.18
Multiplane Copy Back Program — S34ML02G1 and S34ML04G1
Figure 29. Multiplane Copy Back Program
Notes
64. Copy Back Program operation is allowed only within the same memory plane.
65. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.
66. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices.
Figure 30. Multiplane Copy Back Program (ONFI 1.0 Protocol)
Note
67. C1A-C2A Column address for page A. C1A is the least significant byte.
68. R1A-R3A Row address for page A. R1A is the least significant byte.
69. C1B-C2B Column address for page B. C1B is the least significant byte.
70. R1B-R3B Row address for page B. R1B is the least significant byte.
71. The block address bits must be the same except for the bit(s) that select the plane.
I/Ox
R/B#
R/B#
I/Ox
tR
tR
tDBSY
tPROG
1
1
00h
Add. (5 cycles)
35h
Col. Add. 1, 2 and Row Add. 1, 2, 3
Source Address on Plane 0
00h
Add. (5 cycles)
35h
Col. Add. 1, 2 and Row Add. 1, 2, 3
Source Address on Plane 1
85h
Add. (5 cycles)
11h
Col. Add. 1, 2 and Row Add. 1, 2, 3
Destination Address
A0 ~ A11 : Fixed ‘Low’
A12 ~ A17 : Fixed ‘Low’
A18
: Fixed ‘Low’
A19 ~ A28 : Fixed ‘Low’
81h
Add. (5 cycles)
Col. Add. 1, 2 and Row Add. 1, 2, 3
Destination Address
A0 ~ A11 : Fixed ‘Low’
A12 ~ A17 : Valid
A18
: Fixed ‘High’
A19 ~ A28 : Valid
10h
70h
Plane 0
(1)
(3)
Data Field
Spare Field
Plane 1
(2)
(3)
Data Field
Spare Field
Source Page
Source Page
Target Page
Target Page
(1) : Copy Back Read on Plane 0
(2) : Copy Back Read on Plane 1
(3) : Multiplane Copy Back Program
(Note 65)
85h
CLE
WE#
ALE
RE#
IOx
C1A C2A R1A
R2A R3A 11h
85h C1B C2B
SR[6]
A
tIPBSY
R1B R2B R3B 10h
tPROG




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