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S34ML01G1 Datasheet(数据表) 44 Page - Cypress Semiconductor

部件型号  S34ML01G1
说明  1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
下载  71 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
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S34ML01G1 Datasheet(HTML) 44 Page - Cypress Semiconductor

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Document Number: 002-00676 Rev. *V
Page 44 of 71
S34ML01G1
S34ML02G1
S34ML04G1
6.13
Multiplane Page Program Operation — S34ML02G1 and S34ML04G1
Figure 22. Multiplane Page Program
Notes
51. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.
52. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices.
Figure 23. Multiplane Page Program (ONFI 1.0 Protocol)
Notes
53. C1A-C2A Column address for page A. C1A is the least significant byte.
54. R1A-R3A Row address for page A. R1A is the least significant byte.
55. D0A-DnA Data to program for page A.
56. C1B-C2B Column address for page B. C1B is the least significant byte.
57. R1B-R3B Row address for page B. R1B is the least significant byte.
58. D0B-DnB Data to program for page B.
59. The block address bits must be the same except for the bit(s) that select the plane.
CLE
ALE
CE#
RE#
R/B#
I/Ox
WE#
R/B#
I/O0~7
Ex.) Address Restriction for Multiplane Page Program
81h
70h
IO
Program Confirm
Command (True)
tDBSY
Col Add 1,2 and Row Add 1,2,3
(2112 byte data)
A0 ~ A11: Valid
A12 ~ A17: Fixed ‘Low’
A18: Fixed ‘Low’
A19 ~ A28: Fixed ‘Low’
Serial Data
Input Command
Column Address Page Row Address
1 up to 2112 byte
Data Serial Input
Program
Command
(Dummy)
11h
10h
Din
N
Din
M
Din
N
Din
M
Col.
Add1
80h
Col.
Add2
Row
Add1
Row
Add2
Row
Add3
tWB
tPROG
tWB
tDBSY
Col.
Add1
Col.
Add2
Row
Add1
Row
Add2
Row
Add3
tWC
Read Staus
Command
tWHR
tPROG
80h
Address & Data Input
11h
Col Add 1,2 and Row Add 1,2,3
(2112 byte data)
A0 ~ A11: Valid
A12 ~ A17: Valid
A18: Fixed ‘High’
A19 ~ A28: Valid
tADL
tADL
81h
Address & Data Input
10h
70h
(Note 51)
CMD
ADDR ADDR
ADDR
ADDR
ADDR
CMD
ADDR ADDR
ADDR
ADDR
ADDR
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
CMD
CMD
80h
C1A
C2A
D0A
R3A
R2A
R1A
D1A
...
DnA
11h
80h
C1B
C2B
D0B
R3B
R2B
R1B
D1B
...
DnB
10h
Cycle Type
DQx
SR[6]
Cycle Type
DQx
SR[6]
A
tADL
tADL
tADL
tIPBSY
tADL
tPROG




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