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S34ML01G1 Datasheet(数据表) 33 Page - Cypress Semiconductor

部件型号  S34ML01G1
说明  1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
下载  71 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
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S34ML01G1 Datasheet(HTML) 33 Page - Cypress Semiconductor

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Document Number: 002-00676 Rev. *V
Page 33 of 71
S34ML01G1
S34ML02G1
S34ML04G1
Figure 10. Ready/Busy Pin Electrical Application
4.3
Write Protect Operation
Erase and program operations are aborted if WP# is driven low during busy time, and kept low for about 100 ns. Switching WP# low
during this time is equivalent to issuing a Reset command (FFh). The contents of memory cells being altered are no longer valid, as
the data will be partially programmed or erased. The R/B# pin will stay low for tRST (similarly to Figure 33 on page 48). At the end of
this time, the command register is ready to process the next command, and the Status Register bit I/O6 will be cleared to 1, while
I/O7 value will be related to the WP# value. Refer to Table 13 on page 22 for more information on device status.
Erase and program operations are enabled or disabled by setting WP# to high or low respectively, prior to issuing the setup
commands (80h or 60h). The level of WP# shall be set tWW ns prior to raising the WE# pin for the set up command, as explained in
Figure 47 and Figure 48 on page 55.
Figure 11. WP# Low Timing Requirements during Program/Erase Command Sequence
Rp vs. tr, tf and Rp vs. ibusy
Rp
ibusy
Busy
Ready
VCC
VOH
VOL
VOL : 0.4V, VOH : 2.4V
Vcc
GND
Device
open drain output
R/B#
CL
300n
200n
100n
= tf (ns)
20
20
20
20
50
= tr (ns)
3m
2m
1m
ibusy [A]
tr,tf [s]
1k
2k
3k
4k
= ibusy (mA)
1.2
2.4
100
150
200
0.8
0.6
Rp (ohm)
@ Vcc = 3.3V, Ta = 25°C, CL=50 pF
Rp value guidence
Rp (min.) =
=
Vcc (Max.) - VOL (Max.)
3.2V
8mA + ∑I L
I OL + I L
Rp(max) is determined by maximum permissible limit of tr.
where
is the sum of the input currents of all devices tied to the R/B# pin.
L
I
t f
t r
Legend
WE#
I/O[7:0]
WP#
Valid
> 100 ns
Sequence
Aborted




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