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S34ML01G1 Datasheet(数据表) 30 Page - Cypress Semiconductor

部件型号  S34ML01G1
说明  1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
下载  71 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
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S34ML01G1 Datasheet(HTML) 30 Page - Cypress Semiconductor

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 30 page
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Document Number: 002-00676 Rev. *V
Page 30 of 71
S34ML01G1
S34ML02G1
S34ML04G1
32-43
M
Device manufacturer (12 ASCII characters)
53h, 50h, 41h, 4Eh, 53h, 49h, 4Fh, 4Eh,
20h, 20h, 20h, 20h
44-63
M
Device model (20 ASCII characters)
S34ML01G1: 53h, 33h, 34h, 4Dh, 4Ch,
30h, 31h, 47h, 31h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h, 20h
S34ML02G1: 53h, 33h, 34h, 4Dh, 4Ch,
30h, 32h, 47h, 31h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h, 20h
S34ML04G1: 53h, 33h, 34h, 4Dh, 4Ch,
30h, 34h, 47h, 31h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h, 20h
64
M
JEDEC manufacturer ID
01h
65-66
O
Date code
00h
67-79
Reserved (0)
00h
Memory Organization Block
80-83
M
Number of data bytes per page
00h, 08h, 00h, 00h
84-85
M
Number of spare bytes per page
40h, 00h
86-89
M
Number of data bytes per partial page
00h, 02h, 00h, 00h
90-91
M
Number of spare bytes per partial page
10h, 00h
92-95
M
Number of pages per block
40h, 00h, 00h, 00h
96-99
M
Number of blocks per logical unit (LUN)
S34ML01G1: 00h, 04h, 00h, 00h
S34ML02G1: 00h, 08h, 00h, 00h
S34ML04G1: 00h, 10h, 00h, 00h
100
M
Number of logical units (LUNs)
01h
101
M
Number of address cycles
4-7
Column address cycles
0-3
Row address cycles
S34ML01G1: 22h
S34ML02G1: 23h
S34ML04G1: 23h
102
M
Number of bits per cell
01h
103-104
M
Bad blocks maximum per LUN
S34ML01G1: 14h, 00h
S34ML02G1: 28h, 00h
S34ML04G1: 50h, 00h
105-106
M
Block endurance
01h, 05h
107
M
Guaranteed valid blocks at beginning of target
01h
108-109
M
Block endurance for guaranteed valid blocks
01h, 03h
110
M
Number of programs per page
04h
111
M
Partial programming attributes
5-7
Reserved
4
1 = partial page layout is partial page data followed by
partial page spare
1-3
Reserved
0
1 = partial page programming has constraints
00h
112
M
Number of bits ECC correctability
01h
113
M
Number of interleaved address bits
4-7
Reserved (0)
0-3
Number of interleaved address bits
S34ML01G1: 00h
S34ML02G1: 01h
S34ML04G1: 01h
114
O
Interleaved operation attributes
4-7
Reserved (0)
3
Address restrictions for program cache
2
1 = program cache supported
1
1 = no block address restrictions
0
Overlapped / concurrent interleaving support
S34ML01G1: 00h
S34ML02G1: 04h
S34ML04G1: 04h
115-127
Reserved (0)
00h
Electrical Parameters Block
Table 3.4 Parameter Page Description (Continued)
Byte
O/M
Description
Values




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