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LT1641-1 数据表(PDF) 15 Page - Linear Technology |
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LT1641-1 数据表(HTML) 15 Page - Linear Technology |
15 / 24 page 15 4251b12f LTC4251B/LTC4251B-1/ LTC4251B-2 FREQUENCY COMPENSATION The LTC4251B/LTC4251B-1/LTC4251B-2 typical frequency compensation network for the analog current limit loop is a series RC (10Ω) and CC connected to VEE. Figure 5 depicts the relationship between the compensation ca- pacitor CC and the MOSFET’s CISS. The line in Figure 5 is used to select a starting value for CC based upon the MOSFET’s CISS specification. Optimized values for CC are shown for several popular MOSFETs. Differences in the optimized value of CC versus the starting value are small. Nevertheless, compensation values should be verified by board level short-circuit testing. As seen in Figure 4 previously, at the onset of a short- circuit event, the input supply voltage can ring dramatically owing to series inductance. If this voltage avalanches the MOSFET, current continues to flow through the MOSFET to the output. The analog current limit loop cannot control this current flow and therefore the loop undershoots. This effect cannot be eliminated by frequency compensation. A zener diode is required to clamp the input supply voltage and prevent MOSFET avalanche. sense resistor. PCB layout should be balanced and sym- metrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. APPLICATIONS INFORMATION SENSE RESISTOR CONSIDERATIONS For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the VEE and SENSE pins are strongly recommended. The drawing in Figure 6 illustrates the correct way of making connections between the LTC4251B/LTC4251B-1/LTC4251B-2 and the TIMING WAVEFORMS System Power-Up Figure 7 details the timing waveforms for a typical power-up sequence in the case where a board is already installed in the backplane and system power is applied abruptly. At time point 1, the supply ramps up, together with UV/OV and VOUT. VIN follows at a slower rate as set by the VIN bypass capacitor. At time point 2, VIN exceeds VLKO and the internal logic checks for VUVHI < UV/OV < VOVLO, TIMER < VTMRL, GATE < VGATEL and SENSE < VCB. When all conditions are met, an initial timing cycle starts and the TIMER capacitor is charged by a 5.8μA current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is then quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < VGATEL and SENSE < VCB must be satisfied before a start-up cycle is allowed to begin. GATE sources 58μA into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET’s threshold, current begins flowing into the load capacitor. At time point 5, the SENSE voltage (VSENSE – VEE ) reaches the VCB threshold and activates the TIMER. The TIMER capacitor Figure 5. Recommended Compensation Capacitor CC vs MOSFET CISS Figure 6. Making PCB Connections to the Sense Resistor W CURRENT FLOW FROM LOAD CURRENT FLOW TO –48V BACKPLANE SENSE RESISTOR TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER TO SENSE TO VEE 4251b12 F06 MOSFET CISS (pF) 4251b12 F05 60 50 40 30 20 10 0 0 2000 4000 6000 8000 IRF530 IRF540 IRF740 IRF3710 MTY100N10E |
类似零件编号 - LT1641-1 |
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类似说明 - LT1641-1 |
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