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LTC3890-1 数据表(PDF) 26 Page - Linear Technology

部件名 LTC3890-1
功能描述  60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC3890-1 数据表(HTML) 26 Page - Linear Technology

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LTC3892/
LTC3892-1/LTC3892-2
26
38921fc
For more information www.linear.com/LTC3892
APPLICATIONS INFORMATION
above the nominal output voltage. When this condition
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously for
aslongastheovervoltageconditionpersists;ifVOUTreturns
to a safe level, normal operation automatically resumes.
AshortedtopMOSFETwillresultinahighcurrentcondition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
Fault Conditions: Overtemperature Protection
Athighertemperatures,orincaseswheretheinternalpower
dissipation causes excessive self heating on chip (such as
DRVCCshorttoground),theovertemperatureshutdowncir-
cuitrywillshutdowntheLTC3892/LTC3892-1/LTC3892-2.
When the junction temperature exceeds approximately
175°C, the overtemperature circuitry disables the DRVCC
LDO, causing the DRVCC supply to collapse and effectively
shuttingdowntheentireLTC3892/LTC3892-1/LTC3892-2
chip. Once the junction temperature drops back to the ap-
proximately 155°C, the DRVCC LDO turns back on. Long-
term overstress (TJ > 125°C) should be avoided as it can
degrade the performance or shorten the life of the part.
Phase-Locked Loop and Frequency Synchronization
The LTC3892/LTC3892-1/LTC3892-2 has an internal
phase-locked loop (PLL) comprised of a phase frequency
detector, a lowpass filter, and a voltage-controlled oscilla-
tor (VCO). This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the PLLIN/MODE pin. The turn-on
of controller 2’s top MOSFET is thus 180° out of phase
with the external clock. The phase detector is an edge
sensitivedigitaltypethatprovideszerodegreesphaseshift
between the external and internal oscillators. This type of
phase detector does not exhibit false lock to harmonics
of the external clock.
If the external clock frequency is greater than the internal
oscillator’sfrequency,fOSC,thencurrentissourcedcontinu-
ously from the phase detector output, pulling up the VCO
input. When the external clock frequency is less than fOSC,
current is sunk continuously, pulling down the VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP, holds the voltage at the VCO input.
Note that the LTC3892/LTC3892-1/LTC3892-2 can only
be synchronized to an external clock whose frequency is
within range of the LTC3892/LTC3892-1/LTC3892-2’s
internal VCO, which is nominally 55kHz to 1MHz. This is
guaranteed to be between 75kHz and 850kHz. Typically,
the external clock (on the PLLIN/MODE pin) input high
threshold is 1.6V, while the input low threshold is 1.1V.
The LTC3892/LTC3892-1/LTC3892-2 is guaranteed to
synchronize to an external clock that swings up to at least
2.5V and down to 0.5V or less.
Rapid phase locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency corresponding to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase lock and
synchronization. Although it is not required that the free-
running frequency be near the external clock frequency,
doingsowillpreventtheoperatingfrequencyfrompassing
through a large range of frequencies as the PLL locks.
FREQ PIN RESISTOR (k)
15
600
800
1000
35 45 55
25
38921 F10
400
200
500
700
900
300
100
0
65 75 85 95 105 115 125
Figure 9. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin


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