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dc2365afa

DEMO MANUAL DC2365A

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

DC2365A SETUP

DC2365A JUMPERS

DC2365A CONNECTORS

DC590/DC2026 Data Collection

Due to the relatively low and somewhat unpredictable

samplerateoftheDC590/DC2026,itsusefulnessislimited

tonoisemeasurementanddatacollectionofslowlymoving

signals. A typical data capture and histogram are shown in

Figure 3.TochangethedefaultsettingsfortheLTC2358-18

in QuikEval, click on the Channel Config button. This will

open the Config Dialog menu of Figure 8. Using the Config

Dialog menu, it is possible to set the input signal range for

each sequence. There is also a button to return QuikEval

to the default DC2365A settings which are optimized for

the default hardware settings of the DC2365A.

Layout

As with any high performance ADC, this part is sensitive

to layout. The area immediately surrounding the ADC on

the DC2365A should be used as a guideline for place-

ment and routing of the various components associated

with the ADC. Here are some things to remember when

laying out a board for the LTC2358-18. A ground plane is

necessary to obtain maximum performance. Keep bypass

capacitors as close to supply pins as possible. Use indi-

vidual low impedance returns for all bypass capacitors.

Use of a symmetrical layout around the analog inputs will

minimize the effects of parasitic elements. Shield analog

input traces with ground to minimize coupling from other

traces. Keep traces as short as possible.

Component Selection

When driving a low noise, low distortion ADC such as the

LTC2358-18,componentselectionisimportantsoastonot

degrade performance. Resistors should have low values

to minimize noise and distortion. Metal film resistors are

recommended to reduce distortion caused by self heating.

Because of their low voltage coefficients, to further reduce

distortion, NP0 or silver mica capacitors should be used.

Any buffer used to drive the LTC2358-18 should have low

distortion and low noise such as the LT1355 or LTC2057.

Definitions

JP1: REF selects INT or EXT reference for the ADC. The

default setting is INT.

JP2: VCCIO sets the output levels at P1 to either 3.3V

or 2.5V. Use 2.5V to interface to the DC890 which is the

default setting. Use 3.3V to interface to the DC2026.

JP3: I/O selects LVDS or CMOS logic levels. The default

setting is CMOS. LVDS is not supported at this time.

JP4: EEPROM is for factory use only. The default position

is WP.

JP5-JP12: Can be used to short either the + or – input of

AIN0-AIN7 to ground. The individual AIN inputs can also

be driven directly through these terminals. The default is

to short the – input of AIN0–AIN7 to ground.

Definitions

P1: DC890 interface is used to communicate with the

DC890 controller.

J1: CLK provides the master clock for the DC2365A when

interfaced to the DC890. This is not used for QuikEval.

J2: FPGA PROGRAM is used to program the FPGA. This

is for factory use only.

J3: JTAG is for factory use only.

J4: DC590/DC2026 interface is used to communicate with

AIN0–AIN7 of the ADC.

J7: Routes the signals of J5 and J6 to AIN0–AIN7.