GENNUM CORPORATION

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8

Fig. 7 PLL_LOCK Output Circuit

Fig. 8 IJI Output Circuit

Fig. 9 SDO/SDO Output Circuit

Fig. 10 Data Input and SYNC_DETECT_DISABLE Circuit

Fig. 11 PCLK_IN Circuit

Fig. 12 RESET Circuit

All on-chip resistors have ±20% tolerance at room temperature.

10k

PLL_LOCK

IJI

10k

5k

30k

A

SDO

SDO

+

-

2k

BIAS

10k

D0 - D19,

SYNC_DETECT_DISABLE

1k

BIAS

5k

PCLK_IN

20k

BIAS

10k

RESET