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HY27UA081G1M 数据表(PDF) 29 Page - Hynix Semiconductor |
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HY27UA081G1M 数据表(HTML) 29 Page - Hynix Semiconductor |
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29 / 43 page  Rev 0.5 / Oct. 2004 29 HY27UA(08/16)1G1M Series HY27SA(08/16)1G1M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Table 15: AC Characteristics for Operation (3.3V Device and 1.8V Device) Alt. Symbol Symbol Parameter 3.3V Device 1.8V Device Unit tALLRL1 tAR1 Address Latch Low to Read Enable Low Read Electronic Signature Min 10 25 ns tALLRL2 tAR2 Read cycle Min 50 80 ns tBHRL tRR Ready/Busy High to Read Enable Low Min 20 ns tBLBH1 tR Ready/Busy Low to Ready/Busy High 1Gb : Dual Die Max 12 15 us tBLBH2 tPROG Program Busy time Max 500 us tBLBH3 tBERS Erase Busy time Max 3 ms tBLBH4 tRST Reset Busy time, during ready Max 5 us Reset Busy time, during read Max 5 us Reset Busy time, during program Max 10 us Reset Busy time, during erase Max 500 us tCLLRL tCLR Command Latch Low to Read Enable Low Min 10 ns tDZRL tIR Data Hi-Z to Read Enable Low Min 0 ns tEHBH tCRY Chip Enable High to Ready/Busy High (CE intercepted read) Max 70+tr(1) ns tEHEL tCEH Chip Enable High to Chip Enable Low(2) Min 100 ns tEHQZ tCHZ Chip Enable High to Output Hi-Z Max 20 ns tELQV tCEA Chip Enable Low to Output Valid Max 45 75 ns tRHBL tRB Read Enable High to Ready/Busy Low Max 100 ns tRHRL tREH Read Enable High to Read Enable Low Read Enable High Hold time Min 15 20 ns tRHQZ tRHZ Read Enable High to Output Hi-Z Min 15 ns Max 30 tRLRH tRP Read Enable Low to Read Enable High Read Enable Pulse Width Min 40 60 ns tRLRL tRC Read Enable Low to Read Enable Low Read Cycle time Min 60 80 ns tRLQV tREA Read Enable Low to Output Valid Read Enable Access time Max 35 60 ns tREADID Read ES(3) Access time 45 60 tWHBH tR Write Enable High to Ready/Busy High Max 12 15 us |
类似零件编号 - HY27UA081G1M |
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类似说明 - HY27UA081G1M |
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