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AM29F017D-90FE 数据表(PDF) 3 Page - SPANSION |
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AM29F017D-90FE 数据表(HTML) 3 Page - SPANSION |
3 / 44 page 2 Am29F017D GENERAL DESCRIPTION The Am29F017D is a 16 Mbit, 5.0 volt-only Flash mem- ory organized as 2,097,152 bytes. The 8 bits of data appear on DQ0–DQ7. The Am29F017D is offered in a 40-pin or 48-pin TSOP package. This device is de- signed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not re- quired for program or erase operations. The device can also be programmed in standard EPROM program- mers. This device is manufactured using AMD’s 0.23 µm process technology, and offers all the features and ben- efits of the 0.32 µm Am29F017B and the 0.5 µm Am29F016C. The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus conten- tion, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls. The device requires only a single 5.0 volt power sup- ply for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Com- mands are written to the command register using stan- dard microprocessor write timings. Register contents serve as input to an internal state-machine that con- trols the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase com- mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. |
类似零件编号 - AM29F017D-90FE |
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类似说明 - AM29F017D-90FE |
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