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ACT2861QI 数据表(PDF) 28 Page - Active-Semi, Inc |
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ACT2861QI 数据表(HTML) 28 Page - Active-Semi, Inc |
28 / 91 page ACT2861QI Rev 2.0, 27-Apr-2018 Innovative PowerTM www.active-semi.com ActiveSwitcherTM is a trademark of Active-Semi Copyright © 2018 Active-Semi, Inc. 28 TH TH is the battery temperature sense input. Connect a negative temperature coefficient thermistor from TH to AGND. This pin provides a constant current output and the voltage at this pin is used to calculate the battery temperature. If temperature sensing is not used, leave TH open and set register bit “DIS_TH” to a 1 nOTG nOTG is the active low OTG enable input. Pulling nOTG low enables OTG mode when I2C bit EN_OTG is set. The nOTG polarity is configurable via NVM to make it active low or active high. Active low is the default. nOTG is 5V compliant. EN_CHG EN_CHG is the active high charge enable input. Pulling EN_CHG high enables the charger. EN_CHG is 5V compliant. nCHG nCHG is an open drain charge status pin. It indicates the charger status. It goes low to indicate that charging is in progress. It goes HI-Z to indicate charging is com- plete or disabled. When fault condition occurs, nCHG blinks at 1HZ. See Charge Status Pin (nCHG) section for list of faults and further description. ICOMP/GPIO ICOMP/GPIO is a dual function pin. It is the OTG mode compensation pin. Connect the compensation compo- nents between ICOMP/GPIO and AGND. If OTG mode is not used, this pin can be programmed to be a GPIO via I2C. A2D This is the A2D input. Connect this pin directly to the voltage to be measured. Note that the ADC full scale input voltage is 2.5V. nIRQ ACT2861 has an interrupt pin to inform the host of any fault conditions. In general, any IC function with a status bit asserts nIRQ pin low if the status changes. The sta- tus changes can be masked by setting their correspond- ing register bits. If nIRQ is asserted low, the fault must be read before the IC deasserts nIRQ. If the fault re- mains after reading the status bits, nIRQ remains as- serted. Refer to the nIRQ Interrupt Pin (nIRQ) section for more details. nIRQ is an open-drain output and should be pulled up to an appropriate supply voltage with a 10kΩ or greater pull-up resistor. nIRQ is 5V compliant SHIPM SHIPM is the SHIP mode pin. If the IC is in SHIP mode, pulling it low for 32ms moves the state machine to the HIZ state which enables IC to startup into either CHARGE mode or OTG mode. If not used, connect SHIPM to AGND. SCL, SDA SCL and SDA are the I2C clock and data pins to the IC They have standard I2C functionality. They are open- drain outputs and each require a pull-up resistor. The pull-up resistor is typically tied to the system’s uP IO pins. The pullup voltage can range from 1.8V to 5.0V. SCL and SDA are open drain and are 5V compliant. PGND The PGND pin is the buck-boost converters’ power ground. The internal FETs connect directly to the PGND pins. The power supply input and output capacitors must connect to the PGND pins. AGND The AGND pin is the IC’s analog ground pin. It is a “quiet” ground pin that is separate and isolated from the high power, high current carrying PGND ground plane. Con- nect the non-power components to AGND. AGND must be Kelvin connected to the PGND pin in a single loca- tion. Exposed PAD The Exposed pad is connected directly to the PGND pins and must be soldered to the top side ground plane. Place thermal vias under the Exposed PAD to improve the IC’s thermal performance. |
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类似说明 - ACT2861QI |
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