6

MT4C16270

Micron Technology, Inc., reserves the right to change products or specifications without notice.

W06.pm5 – Rev. 10/96

©1996, Micron Technology, Inc.

MT4C16270

256K x 16 DRAM

TECHNOLOGY, INC.

TRUTH TABLE

ADDRESSES

FUNCTION

RAS#

CASL#

CASH#

WE#

OE#

DQs

NOTES

Standby

H

H

→XH→X

X

X

X

X

High-Z

READ: WORD

L

L

L

H

L

ROW

COL

Data-Out

READ: LOWER BYTE

L

L

H

H

L

ROW

COL

Lower Byte, Data-Out

Upper Byte, High-Z

READ: UPPER BYTE

L

H

L

H

L

ROW

COL

Lower Byte, High-Z

Upper Byte, Data Out

WRITE: WORD

L

L

L

L

X

ROW

COL

Data-In

(EARLY WRITE)

WRITE: LOWER

L

L

H

L

X

ROW

COL

Lower Byte, Data-In

BYTE (EARLY)

Upper Byte, High-Z

WRITE: UPPER

L

H

L

L

X

ROW

COL

Lower Byte, High-Z

BYTE (EARLY)

Upper Byte, Data-In

READ WRITE

L

L

L

H

→LL→H ROW COL

Data-Out, Data-In

1, 2

EDO-PAGE-

1st Cycle

L

H

→LH→L

H

L

ROW

COL

Data-Out

2

MODE READ

2nd Cycle

L

H

→LH→L

H

L

n/a

COL

Data-Out

2

Any Cycle

L

L

→HL→H

H

L

n/a

n/a

Data-Out

2

EDO-PAGE-

1st Cycle

L

H

→LH→L

L

X

ROW

COL

Data-In

1

MODE WRITE 2nd Cycle

L

H

→LH→L

L

X

n/a

COL

Data-In

1

EDO-

1st Cycle

L

H

→LH→LH→LL→H ROW COL

Data-Out, Data-In

1, 2

PAGE-MODE

2nd Cycle

L

H

→LH→LH→LL→H

n/a

COL

Data-Out, Data-In

1, 2

READ-WRITE

HIDDEN

READ

L

→H→L

L

L

H

L

ROW

COL

Data-Out

2

REFRESH

WRITE

L

→H→L

L

L

L

X

ROW

COL

Data-In

1, 3

RAS#-ONLY REFRESH

L

H

H

X

X

ROW

n/a

High-Z

CBR REFRESH

H

→L

L

L

X

X

X

X

High-Z

4

NOTE:

1. These WRITE cycles may also be BYTE WRITE cycles (either CASL# or CASH# active).

2. These READ cycles may also be BYTE READ cycles (either CASL# or CASH# active).

3. EARLY WRITE only.

4. At least one of the two CAS# signals must be active (CASL# or CASH#).