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TC90A58F 数据表(PDF) 8 Page - Toshiba Semiconductor |
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TC90A58F 数据表(HTML) 8 Page - Toshiba Semiconductor |
8 / 36 page TC90A58F 2002-02-06 8 (4) Output format in Standard 4:4:1 Mode ROUT[7:0] Y07-0 Y17-0 Y27-0 Y37-0 Y47-0 Y57-0 Y67-0 GOUT[7:6] Cb07-6 Cb05-4 Cb03-2 Cb01-0 Cb47-6 Cb45-4 Cb43-2 GOUT[5:4] Cr07-6 Cr05-4 Cr03-2 Cr01-0 Cr47-6 Cr45-4 Cr43-2 GOUT[3:0] Hi-Z BOUT[7] TRG BOUT[6:0] Hi-Z (5) Output format in Special 4:1:1 Mode ROUT[7:0] Y07-0 Y17-0 Y27-0 Y37-0 Y47-0 Y57-0 Y67-0 GOUT[7:6] Cb03-2 Cb07-6 Cr23-2 Cr27-6 Cb43-2 Cb47-6 Cb63-2 GOUT[5:4] Cb01-0 Cb05-4 Cr21-0 Cr25-4 Cb41-0 Cb45-4 Cb61-0 GOUT[3:0] Hi-Z BOUT[7] TRG BOUT[6:0] Hi-Z Note1: In the above format, 1-data cycle is the main clock (MCK). (For example, when the clock generated by HPLL is 29.82 MHz, MCK = 29.82 MHz) (6) Output format in ITU-R601 16-Bit Mode (data rate: 13.5 MHz) ROUT[7:0] Y07-0 Y17-0 Y27-0 Y37-0 Y47-0 Y57-0 Y67-0 Y77-0 GOUT[7:0] Cb07-0 Cr07-0 Cb27-0 Cr27-0 Cb47-0 Cr47-0 Cb67-0 Cr67-0 BOUT[7:0] Hi-Z (7) Output format in ITU-R601 8-Bit Mode (data rate: 27 MHz) ROUT[7:0] Cb07-0 Y07-0 Cr07-0 Y17-0 Cb27-0 Y27-0 Cr27-0 Y37-0 GOUT[7:0] Hi-Z BOUT[7:0] Hi-Z (8) ITU-R656 Adds SAV and EAV (H, V and F information) to the data in format 7 and outputs the result. 3. Y Signal Delay Circuit The circuit can delay the Y signal by 0 to 14 clocks in relation to the C signal. The delay can be set in the bits YDLY3~YDLY0 of the I2C bus register Sub-Address 17H. 4. Color Bar Generator Color bars for both NTSC and PAL can only be generated internally in ITU-R656 or ITU-R601 (either 8- or 16-bit) Mode. The color bar mode can be set in the BAR bit of the I2C bus register Sub-Address 2AH. |
类似零件编号 - TC90A58F |
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类似说明 - TC90A58F |
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