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CY621472GN 数据表(PDF) 14 Page - Cypress Semiconductor

部件名 CY621472GN
功能描述  4-Mbit (256K words 횞 16 bit) Static RAM
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY621472GN 数据表(HTML) 14 Page - Cypress Semiconductor

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Document Number: 002-10624 Rev. *D
Page 14 of 20
CY62147GN/CY621472GN MoBL®
Figure 12. Write Cycle No. 4 (BHE/BLE Controlled)[32, 33, 34]
Switching Waveforms (continued)
DATAIN VALID
ADDRESS
CE
WE
DATA I/O
tWC
tSCE
tAW
tSA
tBW
tHA
tHD
tHZWE
tSD
BHE/
BLE
tPWE
tLZWE
Notes
32. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
33. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
34. Data I/O is in a HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.


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