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TMP112X 数据表(PDF) 6 Page - Texas Instruments |
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TMP112X 数据表(HTML) 6 Page - Texas Instruments |
6 / 32 page 6 TMP112 SBOS473F – MARCH 2009 – REVISED FEBRUARY 2018 www.ti.com Product Folder Links: TMP112 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated 6.6 Timing Requirements See the Two-Wire Timing Diagrams section for timing diagrams. FAST MODE HIGH-SPEED MODE UNIT MIN MAX MIN MAX ƒ(SCL) SCL operating frequency V+ 0.001 0.4 0.001 2.85 MHz t(BUF) Bus-free time between STOP and START condition See Figure 10 600 160 ns t(HDSTA) Hold time after repeated START condition. After this period, the first clock is generated. 600 160 ns t(SUSTA) repeated start condition setup time 600 160 ns t(SUSTO) STOP condition setup time 600 160 ns t(HDDAT) Data hold time 100 900 25 105 ns t(SUDAT) Data setup time 100 25 ns t(LOW) SCL-clock low period V+ , see Figure 10 1300 210 ns t(HIGH) SCL-clock high period See Figure 10 600 60 ns tFD Data fall time See Figure 10 300 80 ns tRD Data rise time See Figure 10 300 ns SCLK ≤ 100 kHz, see Figure 10 1000 ns tFC Clock fall time See Figure 10 300 40 ns tRC Clock rise time See Figure 10 300 40 ns |
类似零件编号 - TMP112X |
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类似说明 - TMP112X |
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