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CAT28C64BP-15T 数据表(PDF) 1 Page - Catalyst Semiconductor |
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CAT28C64BP-15T 数据表(HTML) 1 Page - Catalyst Semiconductor |
1 / 12 page 1 CAT28C64B 64K-Bit CMOS PARALLEL E2PROM FEATURES s Fast Read Access Times: – 120/150ns s Low Power CMOS Dissipation: – Active: 25 mA Max. – Standby: 100 µA Max. s Simple Write Operation: – On-Chip Address and Data Latches – Self-Timed Write Cycle with Auto-Clear s Fast Write Cycle Time: – 5ms Max. s CMOS and TTL Compatible I/O s Hardware and Software Write Protection DESCRIPTION The CAT28C64B is a fast, low power, 5V-only CMOS Parallel E2PROM organized as 8K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28C64B features hardware and software write pro- tection. 5094 FHD F02 ADDR. BUFFER & LATCHES ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION CONTROL LOGIC TIMER ROW DECODER COLUMN DECODER HIGH VOLTAGE GENERATOR A5–A12 CE OE WE A0–A4 I/O0–I/O7 I/O BUFFERS 8,192 x 8 E2PROM ARRAY 32 BYTE PAGE REGISTER VCC DATA POLLING AND TOGGLE BIT BLOCK DIAGRAM s Commercial, Industrial and Automotive Temperature Ranges s Automatic Page Write Operation: – 1 to 32 Bytes in 5ms – Page Load Timer s End of Write Detection: – Toggle Bit – DATA DATA DATA DATA DATA Polling s 100,000 Program/Erase Cycles s 100 Year Data Retention The CAT28C64B is manufactured using Catalyst’s ad- vanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC- approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC, or, 32- pin PLCC package . © 1999 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 25006-0A 2/98 P-1 |
类似零件编号 - CAT28C64BP-15T |
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类似说明 - CAT28C64BP-15T |
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