数据搜索系统,热门电子元器件搜索 |
|
DS2422 数据表(PDF) 42 Page - Dallas Semiconductor |
|
DS2422 数据表(HTML) 42 Page - Dallas Semiconductor |
42 / 48 page DS2422 42 of 48 The sum of tRL + d (rise rime) on one side and the internal timing generator of the DS2422 on the other side define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a read from the data line. For most reliable communication, tRL should be as short as permissible and the master should read close to but no later than tMSRMAX. After reading from the data line, the master must wait until tSLOT is expired. This guarantees sufficient recovery time tREC for the DS2422 to get ready for the next time slot. IMPROVED NETWORK BEHAVIOR In a 1-Wire environment line termination is possible only during transients controlled by the bus master (1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and topology of the network, reflections from end points and branch points can add up or cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the 1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization with the master and, as a consequence, result in a search ROM command coming to a dead end or cause a device-specific function command to abort. For better performance in network applications, the DS2422 uses a new 1-Wire front end, which makes it less sensitive to noise and also reduces the magnitude of noise injected by the slave device itself. The 1-Wire front end of the DS2422 differs from traditional slave devices in four characteristics. 1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line impedance than a digitally switched transistor, converting the high frequency ringing known from traditional devices into a smoother low-bandwidth transition. The slew rate control is specified by the parameter tFPD, which has different values for standard and Overdrive speed. 2) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot. This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed. 3) There is a hysteresis at the low-to-high switching threshold VTH. If a negative glitch crosses VTH but doesn’t go below VTH - VHY, it will not be recognized (Figure 17, Case A). The hysteresis is effective at any 1-Wire speed. 4) There is a time window specified by the rising edge hold-off time tREH during which glitches will be ignored, even if they extend below VTH - VHY threshold (Figure 17, Case B, tGL < tREH). Deep voltage droops or glitches that appear late after crossing the VTH threshold and extend beyond the tREH window cannot be filtered out and will be taken as beginning of a new time slot (Figure 17, Case C, tGL ³ tREH). Only devices which have the parameters tFPD, VHY and tREH specified in their electrical characteristics use the improved 1-Wire front end. Figure 17. Noise Suppression Scheme VPUP VTH VHY 0V tREH tGL tREH tGL Case A Case C Case B CRC GENERATION With the DS2422 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is an 8-bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2422 to determine if the ROM data has been received error-free. The equivalent polynomial function of this CRC is: X 8 + X5 + X4 + 1. This 8-bit CRC is received in the true (non-inverted) form. It is computed at the factory and lasered into the ROM. The other CRC is a 16-bit type, generated according to the standardized CRC16-polynomial function x 16 + x15 + x2 + 1. This CRC is used for error detection when reading register pages or the datalog memory using the Read Memory with CRC command and for fast verification of a data transfer when writing to or reading from the scratchpad. In contrast to the 8-bit CRC, the 16-bit CRC is always communicated in the inverted form. A CRC- generator inside the DS2422 chip (Figure 18) will calculate a new 16-bit CRC as shown in the command flow chart of Figure 12. The bus master compares the CRC value read from the device to the one it calculates from the data |
类似零件编号 - DS2422 |
|
类似说明 - DS2422 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |