ML145506

LANSDALE Semiconductor, Inc.

DEVICE DESCRIPTIONS

A codec–filter is a device which is used for digitizing and

reconstructing the human voice. These devices were devel-

oped primarily for the telephone network to facilitate voice

switching and transmission. Once the voice is digitized, it may

be switched by digital switching methods or transmitted long

distance (T1, microwave, satellites, etc.) without degradation.

The name codec is an acronym from “coder” for the A/D used

to digitize voice, and “decoder” for the D/A used for recon-

structing voice. A codec is a single device that does both the

A/D and D/A conversions.

To digitize intelligible voice requires a signal to distortion of

about 30 dB for a dynamic range of about 40 dB. This may be

accomplished with a linear 13–bit A/D and D/A, but will far

exceed the required signal to distortion at amplitudes greater

than 40 dB below the peak amplitude. This excess perform-

ance is at the expense of data per sample. Two methods of data

reduction are implemented by compressing the 13–bit linear

scheme to companded 8–bit schemes. These companding

schemes follow a segmented or “piecewise–linear” curve for-

matted as a sign bit, 3 chord bits, and 4 step bits. For a given

chord, all 16 of the steps have the same voltage weighting. As

the voltage of the analog input increases, the 4 step bits incre-

ment and carry to the 3 chord bits which increment. With the

chord bits incremented, the step bits double their voltage

weighting. This results in an effective resolution of 6 bits (sign

+ chord + 4 step bits) across a 42 dB dynamic range (7 chords

above 0, by 6 dB per chord). There are two companding

schemes used; Mu–255 Law specifically in North America,

and A–Law specifically in Europe. These companding schemes

are accepted world wide. The tables show the linear quantiza-

tion levels to PCM words for the two companding schemes.

In a sampling environment, Nyquist theory says that to prop-

erly sample a continuous signal, it must be sampled at a fre-

quency higher than twice the signal’s highest frequency com-

ponent. Voice contains spectral energy above 3 kHz, but its

absence is not detrimental to intelligibility. To reduce the digi-

tal data rate, which is proportional to the sampling rate, a sam-

ple rate of 8 kHz was adopted, consistent with a band-width of

3 kHz. This sampling requires a low–pass filter to limit the

high frequency energy above 3 kHz from distorting the inband

signal. The telephone line is also subject to 50/60 Hz power

line coupling which must be attenuated from the signal by a

high–pass filter before the A/D converter. The D/A process

reconstructs a staircase version of the desired inband signal

which has spectral images of the in-band signal modulated

about the sample frequency and its harmonics. These spectral

images are called aliasing components which need to be atten-

uated to obtain the desired signal. The low–pass filter used to

attenuate these aliasing components is typically called a recon-

struction or smoothing filter.

The ML1455xx series PCM codec–filters have the codec,

both presampling and reconstruction filters, a precision volt-

age reference on chip, and require no external components.

ML145506

The ML145506 PCM codec–filter is the full–featured

22–pin device. It is intended for use in applications requiring

maximum flexibility. The ML145506 is intended for bit inter-

leaved or byte interleaved applications with data clock frequen-

cies which are nonstandard or time varying. One of the five

standard frequencies (listed in CCI Convert Clock Input sec-

tion) is applied to the CCI input, and the data clock inputs can

be any frequency between 64 kHz and 4.096 MHz. The Vref

pin allows for use of an external shared reference or selection

of the internal reference. The RxG pin accommodates gain

adjustments for the inverted analog output. All three pins of the

input gain setting operational amplifier are present which pro-

vide maximum flexibility for the analog interface.

PIN DESCRIPTIONS

DIGITAL

VLS

Logic Level Select Input and HCMOS Digital Ground

VLS controls the logic levels and digital ground reference

for all digital inputs and the digital output. These devices can

operate with logic levels from full supply (VSS to VDD) or

with TTL logic levels using VLS as digital ground. For

VLS = VDD, all I/O is full supply (VSS to VDD swing) with

CMOS switch points. For VSS < VLS < (VDD – 4 V), all

inputs are TTL compatible with VLS being the digital ground

while TDD outputs HCMOS levels from VLS to VDD. The

pins controlled by VLS are inputs MSI, CCI, TDE, TDC, RCE,

RDC, RDD, PDI, and output TDD.

MSI

Master Synchronization Input

MSI is used for determining the sample rate of the transmit

side and as a time base for selecting the internal prescale

divider for the convert clock input (CCI) pin. The MSI pin

should be tied to an 8 kHz clock which may be a frame sync or

system sync signal. MSI has no relation to transmit or receive

data timing, except for determining the internal transmit strobe

as described under the TDE pin description. MSI should be

derived from the transmit timing in asynchronous applications.

In many applications, MSI can be tied to TDE.

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