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BCM20705 数据表(PDF) 41 Page - Cypress Semiconductor |
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BCM20705 数据表(HTML) 41 Page - Cypress Semiconductor |
41 / 51 page Document Number: 002-14867 Rev. *F Page 41 of 51 CYW20705 9.2.2 USB Full-Speed Timing Table 21 through Table 26 shows timing specifications for VDD_USB = 3.3V, VSS = 0V, and TA = 0 to 85oC operating temperature range. Figure 11. USB Full-Speed Timing 9.2.3 UART Timing Figure 12. UART Timing Table 21. USB Full-Speed Timing Specifications Reference Characteristics Minimum Maximum Unit 1 Transition rise time 4 20 ns 2 Transition fall time 4 20 ns 3 Rise/fall timing matching 90 111 % 4 Full-speed data rate 12 – 0.25% 12 + 0.25% Mb/s Table 22. UART Timing Specifications Reference Characteristics Minimum Maximum Unit 1 Delay time, UART_CTS_N low to UART_TXD valid – 24 Baudout cycles 2 Setup time, UART_CTS_N high before midpoint of stop bit – 10 ns 3 Delay time, midpoint of stop bit to UART_RTS_N high – 2 Baudout cycles D+ D- V CRS 90% 90% 10% 10% 1 2 1 3 2 UART_CTS_N UART_TXD UART_RXD UART_RTS_N Midpoint of STOP bit Midpoint of STOP bit |
类似零件编号 - BCM20705 |
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类似说明 - BCM20705 |
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