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Page 5 of 11

Issue A

LANSDALE Semiconductor, Inc.

ML12210

PROGRAMMABLE DIVIDER

19–bit serial data format for the programmable divider is shown below. If the control bit is LOW, data is transferred from the 18–bit shift

register into the 18–bit latch which specifies the swallow A–counter divide ratio (0 to 127) and the programmable N–counter divide ratio

(16 to 2047). An N–counter divide ratio less than 16 is prohibited.

For Control bit (C) = LOW:

SETTING BITS FOR

DIVIDE RATIO OF

SWALLOW A–COUNTER

C

A

1

A

2

A

3

A

4

A

5

A

6

A

7

N

8

N

9

N

10

N

11

N

12

N

13

N

14

N

15

LSB

MSB (FIRST BIT)

CONTROL BIT (LAST BIT)

N

16

N

17

N

18

SETTING BITS FOR

DIVIDE RATIO OF

PROGRAMMABLE N–COUNTER

DIVIDE RATIO OF PROGRAMMABLE N–COUNTER

DIVIDE RATIO OF SWALLOW A–COUNTER

Divide

Ratio N

N

18

N

17

N

16

N

15

N

14

N

13

N

12

N

11

N

10

N

9

N

8

Divide

Ratio A

A

7

A

6

A

5

A

4

A

3

A

2

A

1

16

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

17

0

0

0

0

0

0

1

0

0

0

1

1

0

0

0

0

0

0

1

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

2047

1

1

1

1

1

1

1

1

1

1

1

127

1

1

1

1

1

1

1

DIVIDE RATIO SETTING

fvco = [(P • N)+A] • fosc ÷ R with A<N

fvco: Output frequency of external voltage controlled oscillator (VCO)

N:

Preset divide ratio of binary 11–bit programmable counter (16 to 2047)

A:

Preset divide ratio of binary 7–bit swallow counter (0 to 127, A<N)

fosc: Output frequency of the external frequency oscillator

R:

Preset divide ratio of binary 14–bit programmable reference counter (8 to 16383)

P:

Preset mode of dual modulus prescaler (32 or 64)

Figure 2. Serial Data Input Timing

N18:MSB

N17

(SW:MSB)

(R14)

N8

A7

(R7)

(R6)

A1

C = CONTROL BIT (LAST BIT)

(R1)

(C = CONTROL BIT (LAST BIT))

ts(D)

th(D)

tCW

ts(C→LE)

tEW

DATA

CLK

LE

NOTES: Programmable reference divider data shown in parenthesis. Data shifted into register on rising edge of CLK.

ts(D) = Setup Time DATA to CLK

ts(D) ≥ 10 ns

th(D) = Hold Time DATA to CLK

th(D) ≥ 20 ns

tCW = CLK Pulse Width

tCW ≥ 30 ns

tEW = LE Pulse Width

tEW ≥ 20 ns

ts(C→LE) = Setup Time CLK to LE

ts(C→LE) ≥ 30 ns