SI5022 datasheet(15/28 Pages) SILABS

部件名	SI5022

功能描述	MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER

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制造商	SILABS [Silicon Laboratories]

网页	http://www.silabs.com

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Si5022/Si5023

Rev. 1.23

15

hysteresis from 3 to 8 dB where a nominal value of

800

Ω adjusts the hysteresis level to approximately

6 dB. Use a value of 500

Ω or 1000 Ω for R1 to provide

3 dB or 8 dB of hysteresis, respectively.

Hysteresis is defined as the ratio of the LOS deassert

level (LOSD) and the LOS assert level (LOSA). The

hysteresis in decibels is calculated as 20log(LOSD/

LOSA).

Figure 6. LOS_LVL Mapping

Figure 7. LOS Signal Hysteresis

Bit Error Rate (BER) Detection

The Si5022/23 uses a proprietary Silicon Laboratories®

algorithm to generate a BER alarm on the BER_ALM

pin and a BER indicator on the BERMON pin. When

enabled, the BER_ALM is asserted if the observed BER

is greater than a user-programmed threshold. Bit error

detection relies on the input data edge timing where

edges occurring outside of the expected event window

are counted as bit errors. The BER threshold is

programmed by applying a voltage to the BER_LVL pin

between 500 mV and 2.25 V corresponding to a BER

from approximately 10–10 and 10–6, respectively. The

voltage present on BER_LVL maps to the BER as

follows:

log10 (BER) = (4 x BER_LVL) – 13; BER_LVL in volts;

BER in bits per second.

The BERMON output is always enabled and functions

as a dynamic analog level that is proportional to the

detected bit error rate. This BERMON indicator can be

used to monitor the quality and error status on the

receive data input channel. The range of operation of

the BER processor is between 1E-09 to 1E-03 as

shown in Figure 8. It is recommended that the

BERMON output be filtered with an active low-pass filter

configuration as shown in Figure 9. The external LPF

may be followed by a voltage comparator or analog-to-

digital converter where constant channel monitoring is

desired.

Data Slicing Level

The Si5022/23 provides the ability to externally adjust

the slicing level for applications that require BER

optimization. Adjustments in slicing level of ±15 mV

(relative to the internally-set input common mode

voltage) are supported. The slicing level is set by

applying a voltage between 0.75 V and 2.25 V to the

SLICE_LVL input. The voltage present on SLICE_LVL

maps to the slicing level as follows:

where VSLICE is the slicing level and VSLICE_LVL is the

voltage applied to the SLICE_LVL pin.

When SLICE_LVL is driven below 500 mV, the slicing

level adjustment is disabled, and the slicing level is set

to the cross-point of the differential input signal.

PLL Performance

The PLL implementation used in the Si5022/23 is fully-

compliant with the jitter specifications proposed for

SONET/SDH equipment by Bellcore GR-253-CORE,

Issue 3, September 2000 and ITU-T G.958.

Jitter Tolerance

The Si5022/23’s tolerance to input jitter exceeds that of

the Bellcore/ITU mask shown in Figure 10. This mask

defines the level of peak-to-peak sinusoidal jitter that

must be tolerated when applied to the differential data

input of the device.

Note: There are no entries in the mask table for the data rate

corresponding to OC-24 as that rate is not specified by

either GR-253 or G.958.

40mV/V

0 mV

0 V

LOS_LVL (V)

30 mV

2.25 V

1.50 V

1.00 V

15 mV

1.875 V

40 mV

2.50 V

9

3

LOS

LOS_LVL

R1

R2

10k

Si5023

CDR

LOS Alarm

Set LOS

Level

V

SLICE

V

SLICE_LVL

1.5 V

–

()

50

-------------------------------------------------------

=

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