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74LVC38APW 数据表(PDF) 8 Page - NXP Semiconductors |
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74LVC38APW 数据表(HTML) 8 Page - NXP Semiconductors |
8 / 14 page 2004 Mar 22 8 Philips Semiconductors Product specification Quad 2-input NAND gate (open drain) 74LVC38A AC WAVEFORMS handbook, full pagewidth MNA700 tPLZ VX (3) nY output nA, nB input VI VCC VM (1) VOL (2) GND tPZL VM (1) Fig.6 The input nA, nB to output nY propagation delays. (1) VM = 1.5 V at VCC ≥ 2.7 V. VM = 0.5VCC at VCC < 2.7 V. (2) VOL and VOH are typical output voltage drop that occur with the output load. (3) VX =VOL + 0.3 V at VCC ≥ 2.7 V. VX =VOL + 0.15 V at VCC < 2.7 V. Fig.7 Load circuitry for switching times. Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. tr =tf ≤ 2.5 ns; when measuring fmax, there is no constraint on tr, tf with 50% duty factor. Note 1. The circuit performs better when RL = 1000 Ω. VCC VEXT VI CL RL 1.2 2 × VCC VCC 30 pF 500 Ω(1) 2.7 6 V 2.7 V 50 pF 500 Ω 3.3 to 3.6 6 V 2.7 V 50 pF 500 Ω handbook, full pagewidth VEXT VCC VI VO MNA616 D.U.T. CL RT RL RL PULSE GENERATOR |
类似零件编号 - 74LVC38APW |
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类似说明 - 74LVC38APW |
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