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74LVC38APW 数据表(PDF) 4 Page - NXP Semiconductors |
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74LVC38APW 数据表(HTML) 4 Page - NXP Semiconductors |
4 / 14 page 2004 Mar 22 4 Philips Semiconductors Product specification Quad 2-input NAND gate (open drain) 74LVC38A handbook, halfpage MNA696 38 1 2 3 4 5 6 7 8 14 13 12 11 10 9 1A 1B 1Y 2A 2B 2Y GND 3Y 3A 3B 4Y 4A 4B VCC Fig.1 Pin configuration SO14 and (T)SSOP14. handbook, halfpage 114 GND(1) 1A VCC 7 2 3 4 5 6 1B 1Y 2A 2B 2Y 13 12 11 10 9 4B 4A 4Y 3B 3A 8 GND Top view 3Y MNA977 Fig.2 Pin configuration (DHVQFN14). (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. handbook, halfpage MNA697 1A 1B 1Y 2 1 3 2A 2B 2Y 5 4 6 3A 3B 3Y 10 9 8 4A 4B 4Y 13 12 11 Fig.3 Logic symbol. handbook, halfpage 2 3 & 1 5 6 & 4 10 8 & 9 MNA698 13 11 & 12 Fig.4 Logic symbol (IEEE/IEC). |
类似零件编号 - 74LVC38APW |
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类似说明 - 74LVC38APW |
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