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SLG46140 数据表(PDF) 61 Page - Dialog Semiconductor |
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SLG46140 数据表(HTML) 61 Page - Dialog Semiconductor |
61 / 170 page 000-0046140-109 Page 60 of 169 SLG46140 Multichannel Input MUX Enable (Controlled By Pin11) <530> 0: Disable (PIN11 can not control) 1: Enable PGA Input Mode Control <531> 0: Single ended 1: Differential input PGA Gain Selection <534:532> 000: 0.25x (For single-ended operation only) 001: 0.5x (For single-ended operation only) 010: 1x 011: 2x 100: 4x 101: 8x (For single-ended and differential operation) 110: 16x (For differential operation only) 111: Reserved PGA power on signal <535> 0: power down 1: power on Note: in ADC wake/sleep dynamic on/off mode, must be set to 0 PGA Pseudo-Differential Mode Enable <536> 0: Disable 1: Enable DAC0 Input Selection <547> 0: From register 1: From DCMP1's input DAC0 8 Bit Register Control <855:548> 00: DAC0 output Is 0 FF: DAC0's output Is 1 V Force ADC Analog Part On <558> 0: Disable 1: Enable PGA Output Enable <559> 0: Disable 1: Enable Table 34. PGA Register Settings Signal Function Register Bit Address Register Definition |
类似零件编号 - SLG46140 |
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类似说明 - SLG46140 |
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