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SLG46108 数据表(PDF) 60 Page - Dialog Semiconductor

部件名 SLG46108
功能描述  GreenPAK Ultra-small Programmable Mixed-signal Matrix
Download  70 Pages
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制造商  DIALOG [Dialog Semiconductor]
网页  http://www.dialog-semiconductor.com/
标志 DIALOG - Dialog Semiconductor

SLG46108 数据表(HTML) 60 Page - Dialog Semiconductor

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SLG46108
reg <268>
LUT3_4 or Pipe delay select
0: LUT3_4
1: Pipe delay
LUT4
reg <284:269>
LUT4_0 data or:
reg <269>
Counter/delay2 mode selection
0: Delay Mode
1: Counter Mode
reg <272:270>
Counter/delay2 Clock Source select
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock
111: Counter1 Overflow
reg <280:273>
Counter/delay2 Control Data
1 – 256 (delay time = (counter control data +1) /freq)
reg <282:281>
Delay2 Mode Select or asynchronous counter reset
00: on both falling and rising edges (for delay &
counter reset)
01: on falling edge only (for delay & counter reset)
10: on rising edge only (for delay & counter reset)
11: no delay on either falling or rising edges / high
level reset for counter mode
reg <283>
Counter2/FSM2’s Q are set to Data or Reset to 0s se-
lection
0: reset to 0
1: set to data
reg <285>
LUT4_0 or counter_2 select
0: LUT4_0
1: Counter2
OSC
reg <286>
Force oscillator on
0: Auto Power on
1: Force Power on
reg <287>
Oscillator frequency control
0: 25 k
1: 2 M
reg <289:288>
Osc clock pre-divider
00: div1
01: div2
10: div4
11: div8
reg <292:290>
internal oscillator divider frequency control 1
000: OSC/1
001: OSC/2
010: OSC/3
011: OSC/4
100: OSC/8
101: OSC/12
110: OSC/24
111: OSC/64
reg <295:293>
internal oscillator divider frequency control 2
000: OSC/1
001: OSC/2
010: OSC/3
011: OSC/4
100: OSC/8
101: OSC/12
110: OSC/24
111: OSC/64
reg <296>
External Clock Source Select
0: Internal Oscillator
1: External Clock from Pin8
reg <297>
Reserved
Register Bit
Address
Signal Function
Register Bit Definition


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