8-5

Schematic Diagram

Typical Applications

Reset Timer (Monostable Operation)

Figure 1 shows the CA555 connected as a reset timer. In this

a transistor on the integrated circuit. Upon closing the “start”

switch, or applying a negative trigger pulse to terminal 2, the

integral timer flip-flop is “set” and releases the short circuit

gized). The action allows the voltage across the capacitor to

voltage across the capacitor equals 2/3 V+, the comparator

resets the flip-flop which in turn discharges the capacitor rap-

idly and drives the output to its low state.

Output Rise Time

-

100

-

-

100

-

ns

Output Fall Time

-

100

-

-

100

-

ns

NOTES:

2. When the output is in a high state, the DC supply current is typically 1mA less than the low state value.

Electrical Specifications

PARAMETER

SYMBOL

TEST CONDITIONS

CA555, LM555

CA555C, LM555C, NE555

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

6

THRESHOLD

7

RESET

DISCHARGE

V-

RESET

DISCHARGE

3

OUTPUT

OUTPUT

FLIP-FLOP

TRIGGER

COMPARATOR

THRESHOLD

COMPARATOR

4.7K

830

4.7K

10K

100

100K

1K

5K

7K

3.9K

8

V+

CONTROL

VOLTAGE

5K

6.8K

5K

4.7K

220

4.7K

5

2

4

1

TRIGGER

NOTE: Resistance values are in ohms.

CA555, CA555C, LM555, LM555C, NE555