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MC100ES6111 数据表(PDF) 2 Page - Motorola, Inc |
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MC100ES6111 数据表(HTML) 2 Page - Motorola, Inc |
2 / 12 page MC100ES6111 MOTOROLA TIMING SOLUTIONS 2 Q8 Q7 Q0 Q1 Figure 1. MC100ES6111 Logic Diagram VCC Q2 Q1 Q0 VCC Q7 Q9 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1234 5678 24 23 22 21 20 19 18 17 16 MC100ES6111 Figure 2. 32–Lead Package Pinout (Top View) VCC VCC Q9 Q8 Q2 0 1 CLKA CLKA CLKB CLKB CLK_SEL VCC VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 VBB Table 1. PIN CONFIGURATION Pin I/O Type Function CLKA, CLKA Input ECL/PECL Differential reference clock signal input CLKB, CLKB Input HSTL Alternative differential reference clock signal input CLK_SEL Input ECL/PECL Active clock input select Q[0–9], Q[0–9] Output ECL/PECL Differential clock outputs VEEa Supply Negative power supply VCC Supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. VBB Output DC Reference voltage output for single ended ECL or PECL operation a. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC). Table 2. FUNCTION TABLE Control Default 0 1 CLK_SEL 0 CLKA, CLKA input pair is active. CLKA can be driven by ECL or PECL compatible signals. CLKB, CLKB input pair is active. CLKB can be driven by HSTL compatible signals. |
类似零件编号 - MC100ES6111 |
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类似说明 - MC100ES6111 |
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