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LTC3728LCGN 数据表(PDF) 9 Page - Linear Technology |
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LTC3728LCGN 数据表(HTML) 9 Page - Linear Technology |
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9 / 32 page  9 LTC3728L/LTC3728LX 3728lxfa Figure 2 FU CTIO AL DIAGRA (Refer to Functional Diagram) OPERATIO Main Control Loop The IC uses a constant frequency, current mode step- down architecture with the two controller channels oper- ating 180 degrees out of phase. During normal operation, each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator, I1, resets the RS latch. The peak inductor current at which I1 resets the RS latch is con- trolled by the voltage on the ITH pin, which is the output of each error amplifier EA. The VOSENSE pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current in- creases, it causes a slight decrease in VOSENSE relative to the 0.8V reference, which in turn causes the ITH voltage to SWITCH LOGIC – + 0.8V 4.8V 5V VIN VIN 4.5V BINH CLK2 CLK1 0.18 µA R6 R5 + – FCB + – – + – + – + VREF INTERNAL SUPPLY 3.3VOUT INTVCC RLP CLP 3V FCB EXTVCC INTVCC SGND (UH PACKAGE PAD) + 5V LDO REG SW SHDN 0.55V TOP BOOST TG CB CIN D1 DB PGND BOT BG INTVCC INTVCC VIN + COUT VOUT 3728 FD/F02 RSENSE R2 + VOSENSE DROP OUT DET RUN SOFT START BOT TOP ON S R Q Q OSCILLATOR PHASE DET PLLFLTR PLLIN FCB EA 0.86V 0.80V OV VFB 1.2 µA 6V R1 – + RC 4(VFB) RST SHDN RUN/SS ITH CC CC2 CSS 4(VFB) 0.86V SLOPE COMP 3mV + – – + SENSE– SENSE+ INTVCC 30k 45k 2.4V 45k 30k I1 I2 B DUPLICATE FOR SECOND CONTROLLER CHANNEL + – – + 50k FIN + – + – + – + – PGOOD VOSENSE1 VOSENSE2 0.86V 0.74V 0.86V 0.74V |
类似零件编号 - LTC3728LCGN |
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类似说明 - LTC3728LCGN |
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