LTC2435CGN datasheet(19/40 Pages) LINER

部件名	LTC2435CGN

功能描述	20-Bit No Latency ADCs with Differential Input and Differential Reference

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制造商	LINER [Linear Technology]

网页	http://www.linear.com

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LTC2435/LTC2435-1

19

24351fa

latched on the 24th rising edge of SCK. On the 24th falling

edge of SCK, the device begins a new conversion. SDO

goes HIGH (EOC = 1) indicating a conversion is in progress.

At the conclusion of the data cycle, CS may remain LOW

and EOC monitored as an end-of-conversion interrupt.

Alternatively, CS may be driven HIGH setting SDO to Hi-Z.

As described above, CS may be pulled LOW at any time in

order to monitor the conversion status.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first rising edge and the

24th falling edge of SCK, see Figure 9. On the rising edge

of CS, the device aborts the data output state and imme-

diately initiates a new conversion. This is useful for sys-

tems not requiring all 24 bits of output data, aborting an

invalid conversion cycle or synchronizing the start of a

conversion.

External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface. The

conversion result is shifted out of the device by an exter-

nally generated serial clock (SCK) signal, see Figure 10. CS

may be permanently tied to ground, simplifying the user

interface or isolation barrier.

External Serial Clock, Single Cycle Operation

(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 8.

The serial clock mode is selected on the falling edge of CS.

To select the external serial clock mode, the serial clock pin

(SCK) must be LOW during each CS falling edge.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

While CS is pulled LOW, EOC is output to the SDO pin.

EOC = 1 while a conversion is in progress and EOC = 0 if

the conversion is over. With CS HIGH, the device auto-

matically enters the sleep state once the conversion is

complete.

When CS is low, the devcice enters the data output mode.

The result is held in the internal static shift register until

the first SCK rising edge is seen while CS is LOW. Data is

shifted out the SDO pin on each falling edge of SCK. This

enables external circuitry to latch the output on the rising

edge of SCK. EOC can be latched on the first rising edge

of SCK and the last bit of the conversion result can be

APPLICATIO S I FOR ATIO

Figure 8. External Serial Clock, Single Cycle Operation

EOC

BIT 23

SDO

SCK

(EXTERNAL)

CS

TEST EOC

LSB

MSB

SIG

BIT 0

BIT 5

BIT 19

BIT 18

BIT 20

BIT 21

BIT 22

SLEEP

DATA OUTPUT

CONVERSION

2435 F08

CONVERSION

= 50Hz REJECTION (LTC2435)

= EXTERNAL OSCILLATOR

= 60Hz REJECTION (LTC2435)

= 50Hz/60Hz REJECTION (LTC2435-1)

Hi-Z

VCC

TEST EOC

VCC

FO

REF+

REF–

SCK

IN+

IN–

SDO

GND

CS

214

3

4

13

5

6

12

1, 7, 8, 9, 10, 15, 16

11

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

1µF

2.7V TO 5.5V

LTC2435/

LTC2435-1

3-WIRE

SPI INTERFACE

类似零件编号 - LTC2435CGN

制造商	部件名	数据表	功能描述
Linear Technology	LTC2435	645Kb / 42P	20-Bit No Latency ADCs with Differential Input and Differential Reference
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LTC2435CGN 数据表(PDF) 19 Page - Linear Technology

LTC2435CGN 数据表(HTML) 19 Page - Linear Technology

类似零件编号 - LTC2435CGN

类似说明 - LTC2435CGN

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LTC2435CGN 数据表(PDF) 19 Page - Linear Technology

LTC2435CGN 数据表(HTML) 19 Page - Linear Technology

类似零件编号 - LTC2435CGN

类似说明 - LTC2435CGN

Html Pages

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