ATWILC1000B-MUT [DATASHEET]

Atmel-42491B-ATWILC1000B-MUT_Datasheet_03/2016

2

4

24

Figure 8-3.

SPI Slave Timing Diagram

Table 8-6.

SPI Slave Timing Parameters

Parameter

Symbol

Min.

Max.

Units

Clock Input Frequency

48

MHz

Clock Low Pulse Width

5

ns

Clock High Pulse Width

5

Clock Rise Time

5

Clock Fall Time

5

Input Setup Time

5

Input Hold Time

5

Output Delay

0

20

Slave Select Setup Time

5

Slave Select Hold Time

5

8.4

SPI Master Interface

ATWILC1000B provides a SPI Master interface for accessing external Flash memory. The SPI Master pins are

mapped as shown in Table 8-7. The TXD pin is same as Master Output, Slave Input (MOSI), and the RXD pin

is same as Master Input, Slave Output (MISO). The SPI Master interface supports all four standard modes of

clock polarity and clock phase shown in Table 8-5. External SPI Flash memory is accessed by a processor

programming commands to the SPI Master interface, which in turn initiates a SPI master access to the Flash.

For more specific instructions refer to ATWILC1000B Programming Guide.