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CC1312R 数据表(PDF) 35 Page - Texas Instruments |
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CC1312R 数据表(HTML) 35 Page - Texas Instruments |
35 / 48 page 35 CC1312R www.ti.com SWRS210 – JANUARY 2018 Submit Documentation Feedback Product Folder Links: CC1312R Detailed Description Copyright © 2018, Texas Instruments Incorporated 6.9 Serial Peripherals and I/O The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and TI's synchronous serial interfaces. The SSIs support both SPI master and slave up to 4 MHz. The SSI modules support configurable phase and polarity. The UARTs implement universal asynchronous receiver and transmitter functions. They support flexible baud-rate generation up to a maximum of 3 Mbps. The I2S interface is used to handle digital audio and can also be used to interface pulse-density modulation microphones (PDM). The I2C interface is also used to communicate with devices compatible with the I2C standard. The I2C interface can handle 100-kHz and 400-kHz operation, and can serve as both master and slave. The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge (configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs have high-drive capabilities, which are marked in bold in Section 4. All digital peripherals can be connected to any digital pin on the device. For more information, see the Technical Reference Manual. 6.10 Battery and Temperature Monitor A combined temperature and battery voltage monitor is available in the CC1312R device. The battery and temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage and respond to changes in environmental conditions as needed. The module contains window comparators to interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can also be used to wake up the device from Standby mode through the Always- On (AON) event fabric. 6.11 µDMA The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA controller has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory when the peripheral is ready to transfer more data. Some features of the µDMA controller include the following (this is not an exhaustive list): • Highly flexible and configurable channel operation of up to 32 channels • Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral • Data sizes of 8, 16, and 32 bits • Ping-pong mode for continuous streaming of data 6.12 Debug The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface. The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG. |
类似零件编号 - CC1312R |
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类似说明 - CC1312R |
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