CDCVF2510A datasheet(9/13 Pages) TI

部件名	CDCVF2510A

功能描述	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

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制造商	TI [Texas Instruments]

网页	http://www.ti.com

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TYPICAL CHARACTERISTICS

3

8

13

18

23

28

33

C(LF) − Load Capacitance − pF

400

200

−400

−600

0

−200

600

38

CLK to Y1−n

CLK to FBOUT

VCC = 3.3 V

fc = 100 MHz

C(LY1−n) = 25 pF || 500 Ω

TA = 25°C

See Notes A, B, and C

3

8

13

18

23

28

33

400

200

−400

−600

0

−200

600

38

VCC = 3.3 V

fc = 133 MHz

C(LY1−n) = 25 pF || 500 Ω

TA = 25°C

See Notes A, B, and C

CLK to Y1−n

CLK to FBOUT

C(LF) − Load Capacitance − pF

50

75

100

125

150

175

200

fc − Clock Frequency − MHz

−100

−150

−250

−300

−350

−400

−200

−50

0

VCC = 3.3 V

C(LY) = 25 pF || 500 Ω

C(LF) = 12 pF || 500 Ω

TA = 25°C

See Notes A, B, and C

CLK to FBOUT

−100

−150

−250

−300

−350

−400

−200

3.1

3.2

3.3

3.4

3.5

−50

0

VCC − Supply Voltage at FBOUT − V

3.6

3

fc = 133 MHz

C(LY) = 25 pF || 500 Ω

C(LF) = 12 pF || 500 Ω

TA = 25°C

See Notes A, B, and C

CLK to FBOUT

CDCVF2510A

SCAS764B – MARCH 2004 – REVISED APRIL 2005

STATIC PHASE ERROR

vs

LOAD CAPACITANCE

Figure 4.

Figure 5.

STATIC PHASE ERROR

vs

SUPPLY VOLTAGE AT FBOUT

CLOCK FREQUENCY

Figure 6.

Figure 7.

A.

Trace length FBOUT to FBIN = 5 mm, ZO = 50Ω

B.

C(LY) = Lumped capacitive load Y1-n

C.

C(LFx) = Lumped feedback capacitance at FBOUT = FBIN

9

类似零件编号 - CDCVF2510A

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Texas Instruments	CDCVF2510A	551Kb / 17P	[Old version datasheet] 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
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