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AD8380 数据表(PDF) 2 Page - Analog Devices

部件名 AD8380
功能描述  Fast, High-Voltage Drive, 6-Channel Output DecDriver Decimating LCD Panel Driver
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD8380 数据表(HTML) 2 Page - Analog Devices

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REV. B
–2–
AD8380–SPECIFICATIONS
(@ 25 C, AVCC = 15 V, DVCC = 3.3 V, TMIN = 0 C, TMAX = 85 C, unless
otherwise noted)
Model
Conditions
Min
Typ
Max
Unit
VIDEO DC PERFORMANCE
1
TMIN to TMAX
VDE
DAC Code = 450 to 800
–7.5
+1
+7.5
mV
VCME
DAC Code = 450 to 800
–3.5
+0.5
+3.5
mV
Scale Factor Error
DAC Code = 0 to 1023
–0.25
+0.25
%
Offset Error
DAC Code = 0 to 1023
–7
+1
+7
mV
REFERENCE INPUTS
VMID Range
2
6
7
7.5
V
VMID Bias Current
3
µA
VFS Range
VFS = 2
× (VREFHI–VREFLO)
1
5
6
V
VREFHI
VREFLO +0.5
AVCC – 2.5
AVCC
V
VREFLO
VMID – 0.5
VREFHI – 2.5 VREFHI – 0.5
V
VREFHI Input Resistance
to VREFLO
3.3
k
VREFLO Bias Current
0.2
µA
VREFHI Input Current
3
VFS = 5 V
750
µA
RESOLUTION
Coding
Binary
10
Bits
DIGITAL INPUT CHARACTERISTICS
Input Data Update Rate
75
Ms/s
Clock to Data Setup Times: t1
1ns
Clock to STSQ Setup Times: t3
1ns
Clock to XFR Setup Times: t5
1ns
Maximum CLK Rise and Fall Time, t7
4ns
Clock to A[0:2] Hold Times: t9
4ns
Clock to Data Hold Times: t2
4ns
Clock to STSQ Hold Times: t4
4ns
Clock to XFR Hold Times: t6
4ns
Clock to A[0:2] Setup Times: t8
1ns
CIN
3pF
IIN
0.6
µA
VIH
2.0
V
VIL
0.8
V
VTH
Threshold Voltage
1.4
V
VIDEO OUTPUT CHARACTERISTICS
Output Voltage Swing
AVCC – VOH, VOL – AVEE
1.1
1.3
V
CLK to VID Delay
4
50% of VIDx
13.5
15.5
17.5
ns
Output Current
30
mA
VIDEO OUTPUT DYNAMIC PERFORMANCE
TMIN to TMAX, VO = 5 V Step,
CL = 150 pF, RS = 25
Data Switching Slew Rate
270
V/
µs
Invert Switching Slew Rate
625
V/
µs
Data Switching Settling Time to 1%
5
26
32
ns
Data Switching Settling Time to 0.25%
35
65
ns
Invert Switching Settling Time to 1%
5
30
40
ns
Invert Switching Settling Time to 0.25%
85
100
ns
CLK Feedthrough
6
2
5
mV p-p
All-Hostile Crosstalk
7
Amplitude
95
mV p-p
Glitch Duration
40
ns
POWER SUPPLY
Supply Rejection (VDE)
+VS = 15 V
± 1 V
1
mV/V
DVCC, Operating Range
3
5.5
V
DVCC, Quiescent Current
22
35
mA
AVCC, Operating Range
9
24
V
Total AVCC Quiescent Current
33
44
mA
STBY AVCC Current
STBY = H
0.5
5
mA
STBY DVCC Current
STBY = H
0.1
5
mA
OPERATING TEMPERATURE RANGE
0
85
°C
NOTES
1For definitions of VDE and VCME, see the Transfer Function section. Scale factor error is expressed as percentage of VFS.
2See Figure 1 for valid ranges of VMID.
3VREFHI Input Current = (VREFHI – VREFLO)/(VREFHI Input Resistance) = 2.5 V/3.3 k
Ω.
4Delay time from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV.
5For best settling time results, use minimum series output resistance, R
S of 25
Ω.
6An output channel is selected, and glitch is monitored as CLK is driven. STSQ and XFR are set to logic low.
7Input data is loaded such that any five output channels change by VFS (i.e., 5 V), and the sixth unselected channel is monitored. Measurement is made for both states of INV.
Specifications subject to change without notice.


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