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ADAV801 数据表(PDF) 35 Page - Analog Devices |
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ADAV801 数据表(HTML) 35 Page - Analog Devices |
35 / 61 page ADAV801 Rev. A | Page 34 of 60 Group Delay and Mute—Address 0001000 (0x08) Table 29. Group Delay and Mute Register Bit Map 7 6 5 4 3 2 1 0 MUTE_SRC GRPDLY6 GRPDLY5 GRPDLY4 GRPDLY3 GRPDLY2 GRPDLY1 GRPDLY0 Table 30. Group Delay and Mute Register Bit Descriptions Bit Name Description MUTE_SRC Soft-mutes the output of the sample rate converter. 0 = No mute. 1 = Soft mute. GRPDLY[6:0] Adds delay to the sample rate converter FIR filter by GRPDLY[6:0] input samples. 0000000 = No delay. 0000001 = 1 sample delay. 0000010 = 2 sample delay. 1111110 = 126 sample delay. 1111111 = 127 sample delay. Receiver Configuration 1—Address 0001001 (0x09) Table 31. Receiver Configuration 1 Register Bit Map 7 6 5 4 3 2 1 0 NOCLOCK RxCLK1 RxCLK0 AUTO_DEEMPH ERR1 ERR0 LOCK1 LOCK0 Table 32. Receiver Configuration 1 Register Bit Descriptions Bit Name Description NOCLOCK Selects the source of the receiver clock when the PLL is not locked. 0 = Recovered PLL clock is used. 1 = ICLK1 is used. RxCLK[1:0] Determines the oversampling ratio of the recovered receiver clock. 00 = RxCLK is a 128 × fS recovered clock. 01 = RxCLK is a 256 × fS recovered clock. 10 = RxCLK is a 512 × fS recovered clock. 11 = Reserved. AUTO_DEEMPH Automatically de-emphasizes the data from the receiver based on the channel status information. 0 = Automatic de-emphasis is disabled. 1 = Automatic de-emphasis is enabled. ERR[1:0] Defines what action the receiver should take, if the receiver detects a parity or biphase error. 00 = No action is taken. 01 = Last valid sample is held. 10 = Invalid sample is replaced with zeros. 11 = Reserved. LOCK[1:0] Defines what action the receiver should take, if the PLL loses lock. 00 = No action is taken. 01 = Last valid sample is held. 10 = Zeros are sent out after the last valid sample. 11 = Soft-mute of the last valid audio sample. |
类似零件编号 - ADAV801_17 |
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类似说明 - ADAV801_17 |
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