REV. 0

–4–

AD74111

TIMING CHARACTERISTICS

(AVDD = 2.5 V

Parameter

Min

Max

Unit

Comments

MASTER CLOCK AND RESET

MCLK High

25

ns

MCLK Low

25

ns

RESET Low

10

ns

DIN Setup Time

5

MCLKS

To

DIN Setup Time

5

MCLKS

To

SERIAL PORT

DCLK High

2

20

ns

DCLK Low

2

20

ns

DFS Delay

5

ns

From DCLK Rising Edge

3

DFS Setup Time

5

ns

To DCLK Falling Edge

DFS Hold Time

15

ns

From DCLK Falling Edge

DOUT Delay

30

ns

From DCLK Rising Edge

DIN Setup Time

5

ns

To DCLK Falling Edge

DIN Hold Time

15

ns

From DCLK Falling Edge

DOUT Three-State

40

ns

From DCLK Rising Edge

4

NOTES

MCLK

RESET

DIN

Figure 1. MCLK and

RESET Timing

MSB

MSB–1

DFS

DCLK

DIN

DOUT

MSB

MSB–2

MSB–1

MSB–2

Figure 2. Serial Port Timing

100 A

100 A

50pF

TO OUTPUT

PIN

DVDD1

2

Figure 3. Load Circuit for Digital Output Timing Specifications