AD73322L_17 datasheet(18/49 Pages) AD

部件名	AD73322L

功能描述	Low Cost, Low Power CMOS General-Purpose Dual Analog Front

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制造商	AD [Analog Devices]

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AD73322L

Rev. A | Page 17 of 48

MCLK

DIVIDER

MCLK

EXTERNAL

SE

RESET

SDIFS

SDI

SERIAL PORT 1

(SPORT 1)

SERIAL REGISTER 1

SCLK

DIVIDER

SCLK

CONTROL

REGISTER

1A

CONTROL

REGISTER

1B

CONTROL

REGISTER

1G

CONTROL

REGISTER

1H

CONTROL

REGISTER

1F

CONTROL

REGISTER

1C

CONTROL

REGISTER

1D

DMCLK INTERNAL

SDOFS1

SDO1

8

3

16

8

2

8

CONTROL

REGISTER

1E

MCLK

DIVIDER

MCLK

EXTERNAL

SE

RESET

SDIFS2

SDI2

SERIAL PORT 2

(SPORT 1)

SERIAL REGISTER 2

SCLK

DIVIDER

SCLK

CONTROL

REGISTER

2A

CONTROL

REGISTER

2B

CONTROL

REGISTER

2G

CONTROL

REGISTER

2H

CONTROL

REGISTER

2F

CONTROL

REGISTER

2C

CONTROL

REGISTER

2D

DMCLK INTERNAL

SDOFS

SDO

8

16

8

2

8

CONTROL

REGISTER

2E

Figure 19. SPORT Block Diagram

ANALOG AND DIGITAL GAIN TAPS

The AD73322L features analog and digital feedback paths

between input and output. The amount of feedback is deter-

mined by the gain setting which is programmed in the control

registers. This feature can typically be used for balancing the

effective impedance between input and output when used in

subscriber line interface circuit (SLIC) interfacing.

Analog Gain Tap

The analog gain tap is configured as a programmable

differential amplifier whose input is taken from the ADC’s

input signal path. The output of the analog gain tap is summed

with the output of the DAC. The gain is programmable using

Control Register F (CRF:0-4) to achieve a gain of −1 to +1 in

32 steps with muting being achieved through a separate control

setting (Control Register F Bit 7). The gain increment per step

is 0.0625. The AGT is enabled by powering-up the AGT control

bit in the power control register (CRC:1). When this bit is

set (=1), CRF becomes an AGT control register with CRF:0-4

holding the AGT coefficient, CRF:5 becomes an AGT enable

and CRF:7 becomes an AGT mute control bit.

Control bit CRF:5 connects/disconnects the AGT output to the

summer block at the output of the DAC section while control

bit CRF:7 overrides the gain tap setting with a mute, (zero gain)

setting. Table 10 shows the gain vs. digital setting for the AGT.

In this table, AGT and DGT weights are given for the case of

VFBNx (connected to the sigma-delta modulator’s positive

input) being at a higher potential than VFBPx (connected to the

sigma-delta modulator’s negative input).

Table 10. Analog Gain Tap Settings

AGTC4

AGTC3

AGTC2

AGTC1

AGTC0

Gain (dB)

0

1.00

0

1

0.9375

0

1

0

0.875

0

1

0.8125

0

1

0

0.75

0

1

0.0625

1

0

−0.0625

1

0

1

−0.875

1

0

−0.9375

1

−1.00

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